Abstract: A circuit for initializing a D-latch of an input/output system. The circuit comprises first and second logic means, the first logic means generating an enable signal coupled to the clock input of the D-latch which changes state from inactive to active at a first time t1 and again at a subsequent time t2, in response to the system write control signal addressed to the D-latch and the system reset signal. The second logic means generates a local data signal, in response to the system reset signal and system data signal, to the data input of the D-latch. The D-latch is reset substantially at time t1 and the system data signal is strobed in the D-latch substantially at time t2.