Patents by Inventor Chieh-Ching Huang

Chieh-Ching Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12014768
    Abstract: A memory circuit includes first and second circuits. The first circuit includes a DRAM array including a plurality of bit lines, and the second circuit includes a computation circuit including a sense amplifier circuit. A boundary layer is positioned between the first and second circuits, and the boundary layer includes a plurality of via structures configured to electrically connect the plurality of bit lines to the sense amplifier circuit.
    Type: Grant
    Filed: January 31, 2022
    Date of Patent: June 18, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chieh Lee, Chia-En Huang, Yi-Ching Liu, Wen-Chang Cheng, Yih Wang
  • Publication number: 20090033346
    Abstract: A group probing over active area (POAA) pads arrangement includes a chip having a set of bonding pads, at least a first set of probing pads and a second set of probing pads. Each of the first set of probing pads and the second set of probing pads are electrically connected to one of the corresponding bonding pads, respectively. And each of the first set of probing pads and the second set of probing pads are interlaced in a diagonal line pattern. According to a concept of grouping and interlacing the probing pads, each bonding pad obtains at least two probing pads. Therefore times of test probing performed on each probing pad are reduced and repeated probe's pressures toward inter metal dielectric (IMD) layers underneath the probing pads are consequently reduced.
    Type: Application
    Filed: July 30, 2007
    Publication date: February 5, 2009
    Inventors: Ping-Chang Wu, Chieh-Ching Huang
  • Publication number: 20080303177
    Abstract: A bonding pad structure including a bonding pad and a passivation layer is described. The bonding pad is disposed on a chip. The passivation layer covers the bonding pad. In addition, the passivation layer has a first opening exposing a bonding region of the bonding pad and a second opening exposing a probing region of the bonding pad, respectively.
    Type: Application
    Filed: June 6, 2007
    Publication date: December 11, 2008
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Ping-Chang Wu, Chieh-Ching Huang, Kuang-Hui Tang
  • Publication number: 20080246144
    Abstract: A method for fabricating a contact pad is disclosed. A first metal layer is disposed on a substrate for serving as a probing region. A second metal layer is disposed on the substrate thereafter to serve as an electrical connection region. Preferably, the first metal layer and the second metal layer are composed of different material and are electrically connected. The present invention uses two different metals to form a probing region and an electrical connection region of a contact pad. The probing region is used for providing a contacting surface for a test probe, whereas the electrical connection region is used for establishing an electrical connection in the later bumping or wire bonding process. By providing a contact pad having two different regions, the present invention is able to achieve probing process while prevent the surface of the contact pad from being damaged by the contact of test probes.
    Type: Application
    Filed: April 3, 2007
    Publication date: October 9, 2008
    Inventors: Ping-Chang Wu, Chieh-Ching Huang
  • Publication number: 20080237854
    Abstract: First, a substrate having a conductor therein is provided. Next, a first dielectric layer is disposed on the conductor and the substrate and a first opening is formed in the first dielectric layer for exposing the conductor. A first metal layer is deposited over the surface of the first dielectric layer and into the first opening. Next, an etching stop layer and a second metal layer are deposited over the surface of the first metal layer, and a pattern transfer process is performed by using a second dielectric layer as a mask to remove a portion of the first metal layer, the etching stop layer, and the second metal layer for exposing the first dielectric layer. A passivation layer is disposed on the second metal layer and the first dielectric layer and a second opening is formed in the passivation layer to expose a portion of the second metal layer.
    Type: Application
    Filed: March 26, 2007
    Publication date: October 2, 2008
    Inventors: Ping-Chang Wu, Chieh-Ching Huang