Patents by Inventor Chieh Chiu

Chieh Chiu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250216431
    Abstract: A capacitance measurement method for a capacitive device is provided. The method includes: providing a wafter, on which the capacitive device is formed, having a set of calibration test pads and a set of test pads; applying a test signal to the set of calibration test pads through a first test path to measure a first capacitance between two calibration test pads; applying the test signal to the set of test pads through a second test path to measure a second capacitance between two test pads; and obtaining a capacitance of the capacitive device by a difference between the first capacitance and the second capacitance.
    Type: Application
    Filed: February 5, 2024
    Publication date: July 3, 2025
    Applicant: United Microelectronics Corp.
    Inventors: Pei Chieh Chiu, Shang-Lin Ying, Ching-Tsung Chen, Cheng-Shu Yeh, Kuang-Chuan Lee, Shing-Ren Sheu
  • Publication number: 20250208670
    Abstract: An electronic device including a first body, a keyboard, a light-emitting touch pad module, a light-transmitting cover and a second body is provided. The first body has a first area and a second area arranged side by side. The keyboard is disposed in the first area. The light-emitting touch pad module is slidably disposed in the second area. The light-transmitting cover is disposed on the second area and covers the light-emitting touch pad module. The light-emitting touch pad module displays a drifting touch area on the light-transmitting cover. The second body is pivotally connected to the first body.
    Type: Application
    Filed: May 30, 2024
    Publication date: June 26, 2025
    Applicant: Acer Incorporated
    Inventors: Hung-Chi Chen, Cheng-Han Lin, Huei-Ting Chuang, Shun-Bin Chen, Yen-Chieh Chiu
  • Publication number: 20250210252
    Abstract: A power inductor includes a coil and an induced magnetic element. The coil includes two outer loop circuit layers and a plurality of insulation spacing layer. The outer loop circuit layers are stacked up and electrically connected to each other. The outer loop circuit layers have an outer connection end apiece. At least one insulation spacing layer is located between the outer loop circuit layers. The induced magnetic element encapsulates the coil and exposes the outer connection end of each of the outer loop circuit layers. The induced magnetic element includes a plurality of ferromagnetic particles. The ferromagnetic particles include an iron-based alloy particle and an insulation film covering the iron-based alloy particle apiece.
    Type: Application
    Filed: December 12, 2024
    Publication date: June 26, 2025
    Inventors: Jui-Min CHUNG, Ming-Chieh CHIU
  • Publication number: 20250166681
    Abstract: An integrated circuit includes a memory cell array, a row decoder configured to generate a first decoder signal, a column decoder configured to generate a second decoder signal and an array of write assist circuits electrically coupled to the row and column decoder and the memory cell array. Each write assist circuit is configured to set an operating voltage of a corresponding memory cell. The operating voltage corresponds to an output signal. Each write assist circuit includes a set of P-type transistors coupled together in parallel and further coupled to a supply voltage, and configured to set the output signal in response to an input control signal, and a first N-type transistor coupled to the set of P-type transistors. A first terminal of the first N-type transistor is configured to receive the input control signal. A second terminal of the first N-type transistor is coupled to the supply voltage.
    Type: Application
    Filed: January 17, 2025
    Publication date: May 22, 2025
    Inventors: Chih-Chieh CHIU, Chia-En HUANG, Fu-An WU, I-Han HUANG, Jung-Ping YANG
  • Publication number: 20250145040
    Abstract: A method for monitoring an electric vehicle charging apparatus is provided. A charging pile that includes a power meter and a processor is used to provide a charging current to an electric vehicle through a charging connector. The power meter detects the charging current to generate an initial current value and an initial power value that correspond to an initial charging time, and a present current value and a present power value that correspond to a present time, so that the processor calculates an initial resistance value and a present resistance value of the charging connector accordingly, and then calculates an estimated present temperature value of the charging connector based on the initial resistance value and the present resistance value. The estimated present temperature value is compared with an over-temperature threshold to determine whether to reduce the charging current.
    Type: Application
    Filed: November 2, 2023
    Publication date: May 8, 2025
    Inventors: Hsien-Ju WU, Chun-Chieh CHIU, Tai-Chang CHEN, Jinn-Feng JIANG, Chia-Lung HUANG, Mei-Jung CHEN
  • Publication number: 20250107081
    Abstract: A memory device includes: an interconnect structure, a staircase structure, a dielectric layer and a stop structure. The interconnect structure is located above a substrate. The staircase structure is located above the interconnect structure. The dielectric layer is located above the interconnect structure and covers the staircase structure. The stop structure is located between the interconnect structure and the staircase structure, and between the interconnect structure and the dielectric layer, and the stop structure has an opening exposing the interconnect structure. The first contact extends through the dielectric layer and the opening, and is connected to the interconnect of the interconnect structure. The middle width of the opening is not equal to the top width of the opening, or the middle width of the opening is not equal to the bottom width of the opening. The memory device may be 3D NAND flash memory with high capacity and high performance.
    Type: Application
    Filed: September 22, 2023
    Publication date: March 27, 2025
    Applicant: MACRONIX International Co., Ltd.
    Inventors: Yuan-Chieh Chiu, Kuan-Ting Lu, Chiung-Kun Huang
  • Publication number: 20250076934
    Abstract: A laptop computer including a system host, a modular platform, a rail structure, and at least one tool is provided. The rail structure is disposed at the system host and the modular platform, and the modular platform slides relative to the system host via the rail structure to be assembled to or detached from the system host. The tool is plugged into or out of the system host, and the tool is located on a sliding path of the modular platform when the tool is assembled to the system host.
    Type: Application
    Filed: January 31, 2024
    Publication date: March 6, 2025
    Applicant: Acer Incorporated
    Inventors: Hung-Chi Chen, Cheng-Han Lin, Huei-Ting Chuang, Po-Yi Lee, Yen-Chieh Chiu, Chao-Di Shen
  • Patent number: 12237050
    Abstract: An integrated circuit includes a memory cell array, a row decoder configured to generate a first decoder signal, a column decoder configured to generate a second decoder signal, and an array of write assist circuits coupled to the row and column decoder and the memory cell array. Each write assist circuit is configured to set an operating voltage of a corresponding memory cell, and generate the output signal in response to a first control signal. The operating voltage corresponds to an output signal. Each write assist circuit includes an AND gate coupled to a programmable voltage tuner. The programmable voltage tuner includes a set of P-type transistors coupled to a first P-type transistor. The set of P-type transistors is coupled together in parallel, and receives a set of select control signals. A first terminal of the first P-type transistor is configured to receive an AND signal from the AND gate.
    Type: Grant
    Filed: July 7, 2022
    Date of Patent: February 25, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Chieh Chiu, Chia-En Huang, Fu-An Wu, I-Han Huang, Jung-Ping Yang
  • Patent number: 12237395
    Abstract: A high electron mobility transistor (HEMT) includes a substrate, a channel layer, a barrier layer and a passivation layer. A contact structure is disposed on the passivation layer and extends through the passivation layer and the barrier layer to directly contact the channel layer. The contact structure includes a metal layer, and the metal layer includes a metal material doped with a first additive. A weight percentage of the first additive in the metal layer is between 0% and 2%.
    Type: Grant
    Filed: February 20, 2022
    Date of Patent: February 25, 2025
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ko-Wei Lin, Chun-Chieh Chiu, Chun-Ling Lin, Shu Min Huang, Hsin-Fu Huang
  • Publication number: 20240347765
    Abstract: There is provided a method of producing LLZO having a cubic crystal phase. The method comprises providing an aqueous phase comprising zirconium (Zr) and lanthanum (La). The aqueous phase has a pH of between 7 and 14. An intermediate is formed, the intermediate comprising crystalline La(OH)3 and amorphous Zr hydroxide from the Zr and the La in the aqueous phase. The intermediate is washed and recovered to obtain a washed intermediate. The washed intermediate is heat treated with a Li precursor at a temperature of from 400 to 850° C. to obtain the LLZO.
    Type: Application
    Filed: August 24, 2022
    Publication date: October 17, 2024
    Inventors: George P. DEMOPOULOS, Hsien-Chieh CHIU
  • Publication number: 20240349493
    Abstract: A method of forming a semiconductor memory device includes the following steps. First of all, a substrate is provided, and a plurality of gates is formed in the substrate, along a first direction. Next, a semiconductor layer is formed on the substrate, covering the gates, and a plug is then in the semiconductor layer, between two of the gates. Then, a deposition process is performed to from a stacked structure on the semiconductor layer. Finally, the stacked structure is patterned to form a plurality of bit lines, with one of the bit lines directly in contact with the plug.
    Type: Application
    Filed: June 26, 2024
    Publication date: October 17, 2024
    Applicants: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Yi-Wei Chen, Hsu-Yang Wang, Chun-Chieh Chiu, Shih-Fang Tzou
  • Publication number: 20240324187
    Abstract: A method of forming a semiconductor memory device includes the following steps. First of all, a substrate is provided, and a plurality of gates is formed in the substrate, along a first direction. Next, a semiconductor layer is formed on the substrate, covering the gates, and a plug is then in the semiconductor layer, between two of the gates. Then, a deposition process is performed to from a stacked structure on the semiconductor layer. Finally, the stacked structure is patterned to form a plurality of bit lines, with one of the bit lines directly in contact with the plug.
    Type: Application
    Filed: June 2, 2024
    Publication date: September 26, 2024
    Applicants: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Yi-Wei Chen, Hsu-Yang Wang, Chun-Chieh Chiu, Shih-Fang Tzou
  • Publication number: 20240290721
    Abstract: A semiconductor structure includes a conductive line, a pad layer, and a barrier layer. The conductive line is embedded in a multi-level interconnect structure. The pad layer is over the conductive line. The barrier layer is between the conductive line and the pad layer. The pad layer is electrically connected to the conductive line through the barrier layer, and the barrier layer includes a first poly-crystalline layer and a second poly-crystalline layer. A boundary is between the first poly-crystalline layer and the second poly-crystalline layer.
    Type: Application
    Filed: April 5, 2024
    Publication date: August 29, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ya-Chin CHIU, Ming-Hsien LIN, Chia-Tung HSU, Lun-Chieh CHIU
  • Patent number: 12068545
    Abstract: An antenna structure includes a first signal source, a second signal source, a first radiator, a second radiator, a third radiator, a first circuit, and a second circuit. The first signal source is used to generate a first wireless signal, and the second signal source is used to generate a second wireless signal. The first radiator is coupled to the first signal source to receive the first wireless signal, and the second radiator is coupled to the second signal source to receive the second wireless signal. The first circuit has a first end coupled to the third radiator and a second end coupled to the first radiator or the first signal source. The second circuit has a first end coupled to the third radiator and a second end coupled to the second radiator or the second signal source.
    Type: Grant
    Filed: August 18, 2023
    Date of Patent: August 20, 2024
    Assignee: HTC Corporation
    Inventors: Cheng-Hung Lin, Szu-Po Wang, Chia-Te Chien, Chun-Chieh Wang, Kang-Ling Li, Chun-Hsien Lee, Yu-Chieh Chiu
  • Patent number: 12058851
    Abstract: A method of forming a semiconductor memory device includes the following steps. First of all, a substrate is provided, and a plurality of gates is formed in the substrate, along a first direction. Next, a semiconductor layer is formed on the substrate, covering the gates, and a plug is then in the semiconductor layer, between two of the gates. Then, a deposition process is performed to from a stacked structure on the semiconductor layer. Finally, the stacked structure is patterned to form a plurality of bit lines, with one of the bit lines directly in contact with the plug.
    Type: Grant
    Filed: May 18, 2023
    Date of Patent: August 6, 2024
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Yi-Wei Chen, Hsu-Yang Wang, Chun-Chieh Chiu, Shih-Fang Tzou
  • Patent number: 12046823
    Abstract: A communication device includes a nonconductive track, an antenna element, a first turning wheel, and a second turning wheel. The antenna element is disposed on the nonconductive track. The first turning wheel and the second turning wheel drive the nonconductive track according to a control signal, so as to adjust the position of the antenna element. The communication device provides an almost omnidirectional radiation pattern.
    Type: Grant
    Filed: April 4, 2022
    Date of Patent: July 23, 2024
    Assignee: HTC CORPORATION
    Inventors: Cheng-Hung Lin, Szu-Po Wang, Chia-Te Chien, Chun-Chieh Wang, Kang-Ling Li, Chun-Hsien Lee, Yu-Chieh Chiu
  • Patent number: 11991882
    Abstract: A method for fabricating a memory device includes: providing a substrate; forming a first dielectric layer over the substrate; forming a plurality of conductive layers and a plurality of dielectric layers alternately and horizontally disposed on the substrate; forming a channel column structure on the substrate and in the plurality of conductive layers and the plurality of dielectric layers, where a side wall of the channel column structure is in contact with the plurality of conductive layers; forming a second dielectric layer covering the first dielectric layer; and forming, in the first and second dielectric layers, a conductive column structure adjacent to the channel column structure and in contact with one of the plurality of conductive layers, where the conductive column structure includes a liner insulating layer as a shell layer.
    Type: Grant
    Filed: November 16, 2021
    Date of Patent: May 21, 2024
    Assignee: MACRONIX International Co., Ltd.
    Inventors: Yao-An Chung, Yuan-Chieh Chiu, Ting-Feng Liao, Kuang-Wen Liu, Kuang-Chao Chen
  • Patent number: 11978703
    Abstract: A semiconductor structure includes a conductive line, a pad layer, and a barrier layer. The conductive line is embedded in a multi-level interconnect structure. The pad layer is over the conductive line. The barrier layer is between the conductive line and the pad layer. The pad layer is electrically connected to the conductive line through the barrier layer, and the barrier layer includes a first poly-crystalline layer and a second poly-crystalline layer. A boundary is between the first poly-crystalline layer and the second poly-crystalline layer.
    Type: Grant
    Filed: November 17, 2022
    Date of Patent: May 7, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ya-Chin Chiu, Ming-Hsien Lin, Chia-Tung Hsu, Lun-Chieh Chiu
  • Patent number: 11925650
    Abstract: The present invention provides an antibacterial chemical compound, its manufacturing method and its use thereof which acts as antibacterial agents being useful for treating a disease or condition characterized by infectious disease, such as gastroenteritis and invasive non-typhoidal Salmonellosis, and also providing a new therapeutic option for patients infected by the bacteria with the resistance to antibiotics.
    Type: Grant
    Filed: March 4, 2022
    Date of Patent: March 12, 2024
    Assignees: NATIONAL TAIWAN UNIVERSITY, NATIONAL YANG MING CHIAO TUNG UNIVERSITY
    Inventors: Hao-Chieh Chiu, Chung-Wai Shiau
  • Patent number: 11914429
    Abstract: An electronic device includes a host, a display, a sliding plate, and a keyboard. The host has an operating surface. The display is pivoted to the host. The sliding plate is slidably disposed in the host, where the display is mechanically coupled to the sliding plate, and the sliding plate includes a plat portion and a recess portion that are arranged side by side. The keyboard is integrated to the host. The keyboard includes a key structure, where the key structure includes a key cap and a reciprocating element, and the key cap is exposed from the operating surface of the host. The reciprocating element is disposed between the key cap and the sliding plate and has a first end connected to the key cap and a second end contacting the sliding plate. The second end is located on a sliding path of the plat portion and the recess portion.
    Type: Grant
    Filed: March 9, 2023
    Date of Patent: February 27, 2024
    Assignee: Acer Incorporated
    Inventors: Hung-Chi Chen, Shun-Bin Chen, Huei-Ting Chuang, Yen-Chieh Chiu, Yu-Wen Lin, Yen-Chou Chueh, Po-Yi Lee