Patents by Inventor Chieh-Chuan Chin

Chieh-Chuan Chin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8483333
    Abstract: A method for adjusting a system clock in terms of an operational status of at least one non-baseband module includes: getting first information corresponding to the system clock required by at least one baseband module, wherein the first information comprises a frequency characteristic of the system clock; getting second information corresponding to the at least one non-baseband module, wherein the second information comprises a frequency characteristic of a radio frequency (RF) signal to be received by the non-baseband module; and selectively adjusting a frequency of the system clock by referring to the first information and the second information.
    Type: Grant
    Filed: December 3, 2010
    Date of Patent: July 9, 2013
    Assignee: Mediatek Inc.
    Inventors: Ming-Jie Yang, Chieh-Chuan Chin, Chien-Sheng Lai, Po-Sen Tseng
  • Publication number: 20110274221
    Abstract: A method for adjusting a system clock in terms of an operational status of at least one non-baseband module includes: getting first information corresponding to the system clock required by at least one baseband module, wherein the first information comprises a frequency characteristic of the system clock; getting second information corresponding to the at least one non-baseband module, wherein the second information comprises a frequency characteristic of a radio frequency (RF) signal to be received by the non-baseband module; and selectively adjusting a frequency of the system clock by referring to the first information and the second information.
    Type: Application
    Filed: December 3, 2010
    Publication date: November 10, 2011
    Inventors: Ming-Jie Yang, Chieh-Chuan Chin, Chien-Sheng Lai, Po-Sen Tseng
  • Patent number: 7327188
    Abstract: An amplifier includes a subtracting unit for generating an error signal according to an input signal and an output signal; a noise shaping unit for executing a noise shaping operation on the error signal to produce a noise-shaped signal; a pulse adjustment unit for generating a control signal according to the noise-shaped signal and the input signal; and a power stage for generating the output signal according to the control signal.
    Type: Grant
    Filed: January 16, 2006
    Date of Patent: February 5, 2008
    Assignee: Realtek Semiconductor Corp.
    Inventors: Wen-Chi Wang, Fu-Yi Hsieh, Yi-Chang Tu, Chieh-Chuan Chin
  • Patent number: 7283081
    Abstract: An application circuit for shaping noises and method thereof involve an analog-to-digital converter which converts a first analog signal into an n-bit digital signal for an encoder to generate a p-bit digital signal. Then a control circuit generates a plurality of control signals based on the p-bit digital signal, wherein p is two to the power of n minus one, and n is an integer greater than one. Each of the (2n?1) unit elements with element mismatch in an internal n-bit digital-to-analog converter executes the digital to analog conversion in response to the corresponding control signal, thereby generating a second analog signal, and an adder outputs the first analog signal based on the second analog signal and a third analog signal.
    Type: Grant
    Filed: April 20, 2006
    Date of Patent: October 16, 2007
    Assignee: Realtek Semiconductor Corp.
    Inventors: Chieh-Chuan Chin, Bing-I Chang, Wen-Chi Wang
  • Publication number: 20070024483
    Abstract: An application circuit and method for shaping noises are provided. In an embodiment, an analog-to-digital converter converts a first analog signal into an n-bit digital signal for an encoder to generate a p-bit digital signal. Then a control circuit generates a plurality of control signals based on the p-bit digital signal, wherein p is two to the power of n minus one, and n is an integer greater than one. Each of the (2n?1) unit elements with element mismatch in an internal n-bit digital-to-analog converter executes the digital to analog conversion in response to the corresponding control signal, thereby generating a second analog signal, and an adder outputs the first analog signal based on the second analog signal and a third analog signal.
    Type: Application
    Filed: April 20, 2006
    Publication date: February 1, 2007
    Inventors: Chieh-Chuan Chin, Bing-I Chang, Wen-Chi Wang
  • Publication number: 20060197590
    Abstract: An amplifier includes a subtracting unit for generating an error signal according to an input signal and an output signal; a noise shaping unit for executing a noise shaping operation on the error signal to produce a noise-shaped signal; a pulse adjustment unit for generating a control signal according to the noise-shaped signal and the input signal; and a power stage for generating the output signal according to the control signal.
    Type: Application
    Filed: January 16, 2006
    Publication date: September 7, 2006
    Inventors: Wen-Chi Wang, Fu-Yi Hsieh, Yi-Chang Tu, Chieh-Chuan Chin