Abstract: An integrated circuit includes a metal/dielectric layer, a second dielectric layer, a bottom electrode, a resistance switch element, and a top electrode. The metal/dielectric layer has a first dielectric layer and a conductive feature in the first dielectric layer. The second dielectric layer is over the metal/dielectric layer. The bottom electrode is over and in contact with the conductive feature and surrounded by the second dielectric layer. The second dielectric layer has a tapered sidewall, a lower portion of the tapered sidewall of the second dielectric layer is covered by the bottom electrode, and an upper portion of the tapered sidewall of the second dielectric layer is free from coverage by the bottom electrode. The resistance switch element is over the bottom electrode. The top electrode is over the resistance switch element.

Abstract: A memory device includes a first bottom electrode, a first memory stack, and a second memory stack. The first bottom electrode has a first portion and a second portion connected to the first portion. The first memory stack is over the first portion of the first bottom electrode. The first memory stack includes a first resistive switching element and a first top electrode over the first resistive switching element. The second memory stack is over the second portion of the first bottom electrode. The second memory stack comprises a second resistive switching element and a second top electrode over the second resistive switching element.

Abstract: A method for fabricating an integrated circuit is provided. The method includes depositing a dielectric layer over a conductive feature; etching an opening in the dielectric layer to expose the conductive feature, such that the dielectric layer has a tapered sidewall surrounding the opening; depositing a bottom electrode layer into the opening in the dielectric layer; depositing a resistance switch layer over the bottom electrode layer; patterning the resistance switch layer and the bottom electrode layer respectively into a resistance switch element and a bottom electrode, in which a sidewall of the bottom electrode is landing on the tapered sidewall of the dielectric layer.

Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a memory device arranged over an etch stop material on a substrate. The memory device includes a data storage structure disposed between a bottom electrode and a top electrode. A first interconnect via contacts an upper surface of the bottom electrode and a second interconnect via contacts an upper surface of the top electrode. An insulating structure is arranged over and along opposing outermost sidewalls of the top electrode. The bottom electrode laterally extends to different non-zero distances past opposing outermost sidewalls of the insulating structure.

Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a memory device arranged over an etch stop material over a substrate. The memory device includes a data storage structure disposed between a bottom electrode and a top electrode. A first interconnect via contacts an upper surface of the bottom electrode and a second interconnect via contacts an upper surface of the top electrode. An interconnect wire contacts a top of the first interconnect via. A third interconnect via contacts a bottom of the interconnect wire and extends through the etch stop material to a plurality of lower interconnects below the etch stop material.

Abstract: A method for fabricating an integrated circuit is provided. The method includes depositing a dielectric layer over a conductive feature; etching an opening in the dielectric layer to expose the conductive feature, such that the dielectric layer has a tapered sidewall surrounding the opening; depositing a bottom electrode layer into the opening in the dielectric layer; depositing a resistance switch layer over the bottom electrode layer; patterning the resistance switch layer and the bottom electrode layer respectively into a resistance switch element and a bottom electrode, in which a sidewall of the bottom electrode is landing on the tapered sidewall of the dielectric layer.

Abstract: A method for fabricating an integrated circuit is provided. The method includes depositing a dielectric layer over a conductive feature; etching an opening in the dielectric layer to expose the conductive feature, such that the dielectric layer has a tapered sidewall surrounding the opening; depositing a bottom electrode layer into the opening in the dielectric layer; depositing a resistance switch layer over the bottom electrode layer; patterning the resistance switch layer and the bottom electrode layer respectively into a resistance switch element and a bottom electrode, in which a sidewall of the bottom electrode is landing on the tapered sidewall of the dielectric layer.

Abstract: A semiconductor device includes a non-volatile memory. The non-volatile memory includes a first dielectric layer disposed on a substrate, a floating gate disposed on the dielectric layer, a control gate, a second dielectric layer disposed between the floating gate and the control gate, sidewall spacers disposed on opposing sides of a stacked structure including the floating gate, the second dielectric layer and the control gate, and an erase gate and a select gate disposed on sides of the stacked structure, respectively. An upper surface of the erase gate and one of the sidewall spacers in contact with the erase gate form an angle ?1 at a contact point of the upper surface of the erase gate and the one of the sidewall spacers, where 90°<?1<115° measured from the upper surface of the erase gate.

Abstract: A semiconductor device includes a non-volatile memory. The non-volatile memory includes a first dielectric layer disposed on a substrate, a floating gate disposed on the dielectric layer, a control gate, a second dielectric layer disposed between the floating gate and the control gate, sidewall spacers disposed on opposing sides of a stacked structure including the floating gate, the second dielectric layer and the control gate, and an erase gate and a select gate disposed on sides of the stacked structure, respectively. An upper surface of the erase gate and one of the sidewall spacers in contact with the erase gate form an angle ?1 at a contact point of the upper surface of the erase gate and the one of the sidewall spacers, where 90°<?1<115° measured from the upper surface of the erase gate.

Abstract: A memory device includes a first bottom electrode, a first memory stack, and a second memory stack. The first bottom electrode has a first portion and a second portion connected to the first portion. The first memory stack is over the first portion of the first bottom electrode. The first memory stack includes a first resistive switching element and a first top electrode over the first resistive switching element. The second memory stack is over the second portion of the first bottom electrode. The second memory stack comprises a second resistive switching element and a second top electrode over the second resistive switching element.

Abstract: A memory device includes a first bottom electrode, a first memory stack, and a second memory stack. The first bottom electrode has a first portion and a second portion connected to the first portion. The first memory stack is over the first portion of the first bottom electrode. The first memory stack includes a first resistive switching element and a first top electrode over the first resistive switching element. The second memory stack is over the second portion of the first bottom electrode. The second memory stack comprises a second resistive switching element and a second top electrode over the second resistive switching element.

Abstract: A method for fabricating an integrated circuit is provided. The method includes depositing a dielectric layer over a conductive feature; etching an opening in the dielectric layer to expose the conductive feature, such that the dielectric layer has a tapered sidewall surrounding the opening; depositing a bottom electrode layer into the opening in the dielectric layer; depositing a resistance switch layer over the bottom electrode layer; patterning the resistance switch layer and the bottom electrode layer respectively into a resistance switch element and a bottom electrode, in which a sidewall of the bottom electrode is landing on the tapered sidewall of the dielectric layer.

Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a memory device arranged over an etch stop material over a substrate. The memory device includes a data storage structure disposed between a bottom electrode and a top electrode. A first interconnect via contacts an upper surface of the bottom electrode and a second interconnect via contacts an upper surface of the top electrode. An interconnect wire contacts a top of the first interconnect via. A third interconnect via contacts a bottom of the interconnect wire and extends through the etch stop material to a plurality of lower interconnects below the etch stop material.

Abstract: In some embodiments, a method for forming a semiconductor device is provided. The method includes forming a pad stack over a semiconductor substrate, where the pad stack includes a lower pad layer and an upper pad layer. An isolation structure having a pair of isolation segments separated in a first direction by the pad stack is formed in the semiconductor substrate. The upper pad is removed to form an opening, where the isolation segments respectively have opposing sidewalls in the opening that slant at a first angle. A first etch is performed that partially removes the lower pad layer and isolation segments in the opening so the opposing sidewalls slant at a second angle greater than the first angle. A second etch is performed to round the opposing sidewalls and remove the lower pad layer from the opening. A floating gate is formed in the opening.

Abstract: A method of manufacturing a non-volatile memory semiconductor device includes forming a plurality of memory cells on a non-volatile memory cell area of a semiconductor substrate, and forming a conductive layer over the plurality of memory cells. A first planarization layer of a planarization material having a viscosity of less than about 1.2 centipoise is formed over the plurality of memory cells. A planarization operation is performed on the first planarization layer and the conductive layer, thereby removing an upper region of the first planarization layer and an upper region of the conductive layer. Portions of a lower region of the conductive layer are completely removed between the memory cells.

Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a lower inter-level dielectric (ILD) structure surrounding a plurality of lower interconnect layers over a substrate. An etch stop material is disposed over the lower ILD structure. A bottom electrode is arranged over an upper surface of the etch stop material, a data storage structure is disposed on an upper surface of the bottom electrode and is configured to store a data state, and a top electrode is disposed on an upper surface of the data storage structure. A first interconnect via contacts the upper surface the bottom electrode and a second interconnect via contacts the top electrode.

Abstract: A semiconductor device includes a non-volatile memory. The non-volatile memory includes a first dielectric layer disposed on a substrate, a floating gate disposed on the dielectric layer, a control gate, a second dielectric layer disposed between the floating gate and the control gate, sidewall spacers disposed on opposing sides of a stacked structure including the floating gate, the second dielectric layer and the control gate, and an erase gate and a select gate disposed on sides of the stacked structure, respectively. An upper surface of the erase gate and one of the sidewall spacers in contact with the erase gate form an angle ?1 at a contact point of the upper surface of the erase gate and the one of the sidewall spacers, where 90°<?1<115° measured from the upper surface of the erase gate.

Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a lower inter-level dielectric (ILD) structure surrounding a plurality of lower interconnect layers over a substrate. An etch stop material is disposed over the lower ILD structure. A bottom electrode is arranged over an upper surface of the etch stop material, a data storage structure is disposed on an upper surface of the bottom electrode and is configured to store a data state, and a top electrode is disposed on an upper surface of the data storage structure. A first interconnect via contacts the upper surface the bottom electrode and a second interconnect via contacts the top electrode.

Abstract: A semiconductor device includes a non-volatile memory. The non-volatile memory includes a first dielectric layer disposed on a substrate, a floating gate disposed on the dielectric layer, a control gate, a second dielectric layer disposed between the floating gate and the control gate, sidewall spacers disposed on opposing sides of a stacked structure including the floating gate, the second dielectric layer and the control gate, and an erase gate and a select gate disposed on sides of the stacked structure, respectively. An upper surface of the erase gate and one of the sidewall spacers in contact with the erase gate form an angle ?1 at a contact point of the upper surface of the erase gate and the one of the sidewall spacers, where 90°<?1<115° measured from the upper surface of the erase gate.

Abstract: A method for forming a semiconductor structure includes providing a substrate including a plurality of first isolation structures formed therein, wherein the first isolation structures are protruded from a surface of the substrate; conformally forming a semiconductor layer over the substrate and the first isolation structures; forming a sacrificial layer over the semiconductor layer to form a planar surface over the substrate; and removing the sacrificial layer, a portion of the semiconductor layer and a portion of each first isolation structure to form at least one first gate structure using a same etchant.