Patents by Inventor Chieh-Han Wu

Chieh-Han Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250105057
    Abstract: An interconnect structure includes a first conductive feature, a first dielectric layer a first etch stop layer, a second etch stop layer, a second dielectric layer, and a second conductive feature. The first etch stop layer is disposed over the first conductive feature and the first dielectric layer. The second etch stop layer is disposed on the first etch stop layer. The second dielectric layer is disposed on the second etch stop layer. The second conductive feature includes a first conductive layer and a first barrier layer. The first conductive layer extends through the second dielectric layer, the second and the first etch stop layers to contact to the first conductive feature. The first barrier layer is sandwiched between the first conductive layer and the second dielectric layer, the first conductive layer and the second etch stop layer, and between the first conductive layer and the first etch stop layer.
    Type: Application
    Filed: September 22, 2023
    Publication date: March 27, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shao-Kuan Lee, Tzu-Hui Wei, Cheng-Hsiung Tsai, Chieh-Han Wu, Yu-Hao Yeh
  • Publication number: 20250087535
    Abstract: A method for forming a semiconductor structure includes following operations. A first metallization feature is formed, and a first cap layer is formed over the first metallization feature. A first insulating layer is formed over the first cap layer and the first metallization feature. A first dielectric structure is formed over the first insulating layer. A portion of the first dielectric structure and a portion of the first insulating layer are removed to expose the first cap layer. A second cap layer is formed over the first cap layer and the first metallization feature. A second insulating layer and a patterned second dielectric structure are formed over the substrate. The patterned second dielectric structure includes a trench and a via opening coupled to a bottom of the trench. A second metallization feature is formed in the trench, and a via structure is formed in the via opening.
    Type: Application
    Filed: November 22, 2024
    Publication date: March 13, 2025
    Inventors: HWEI-JAY CHU, CHIEH-HAN WU, CHENG-HSIUNG TSAI, CHUNG-JU LEE
  • Patent number: 12165920
    Abstract: A semiconductor structure includes a first metallization feature, a first dielectric structure over the first metallization feature, a second metallization feature embedded in the first dielectric structure, a via structure between the first metallization feature and the second metallization feature, and a first insulating layer between the first dielectric structure and the first metallization feature, and between the first dielectric structure and the via structure. The first metallization feature extends along a first direction, and the second metallization feature extends along a second direction different from the first direction. The first insulating layer covers first sidewalls of the via structure along the second direction.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: December 10, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Hwei-Jay Chu, Chieh-Han Wu, Cheng-Hsiung Tsai, Chung-Ju Lee
  • Publication number: 20240379437
    Abstract: A semiconductor structure includes a first metallization feature, a first dielectric structure over the first metallization feature, a second metallization feature embedded in the first dielectric structure, a via structure between the first metallization feature and the second metallization feature, and a first insulating layer between the first dielectric structure and the first metallization feature, and between the first dielectric structure and the via structure. The first metallization feature extends along a first direction, and the second metallization feature extends along a second direction different from the first direction. The first insulating layer covers first sidewalls of the via structure along the second direction.
    Type: Application
    Filed: July 25, 2024
    Publication date: November 14, 2024
    Inventors: HWEI-JAY CHU, CHIEH-HAN WU, CHENG-HSIUNG TSAI, CHUNG-JU LEE
  • Publication number: 20240339396
    Abstract: Interconnect structures and methods of forming the same are provided. An interconnect structure according to the present disclosure includes a conductive line feature over a substrate, a conductive etch stop layer over the conductive line feature, a contact via over the conductive etch stop layer, and a barrier layer disposed along a sidewall of the conductive line feature, a sidewall of the conductive etch stop layer, and a sidewall of the contact via.
    Type: Application
    Filed: June 17, 2024
    Publication date: October 10, 2024
    Inventors: Chieh-Han Wu, Cheng-Hsiung Tsai, Chih Wei Lu, Chung-Ju Lee
  • Patent number: 12046551
    Abstract: Interconnect structures and methods of forming the same are provided. An interconnect structure according to the present disclosure includes a conductive line feature over a substrate, a conductive etch stop layer over the conductive line feature, a contact via over the conductive etch stop layer, and a barrier layer disposed along a sidewall of the conductive line feature, a sidewall of the conductive etch stop layer, and a sidewall of the contact via.
    Type: Grant
    Filed: April 17, 2023
    Date of Patent: July 23, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chieh-Han Wu, Cheng-Hsiung Tsai, Chih Wei Lu, Chung-Ju Lee
  • Publication number: 20240021472
    Abstract: An interconnection structure, along with methods of forming such, are described. The structure includes a first conductive feature having a first thickness, a first dielectric material disposed adjacent the first conductive feature, and the first dielectric material has a second thickness greater than the first thickness. The structure further includes a second conductive feature disposed adjacent the first dielectric material, a first etch stop layer disposed on the first conductive feature, a second etch stop layer disposed on the first dielectric material, and a second dielectric material disposed on the first etch stop layer and the second etch stop layer. The second dielectric material is in contact with the first dielectric material.
    Type: Application
    Filed: May 28, 2023
    Publication date: January 18, 2024
    Inventors: Hwei-Jay CHU, Chieh-Han WU, Hsin-Chieh YAO, Cheng-Hsiung TSAI, Chung-Ju LEE
  • Patent number: 11830910
    Abstract: A method for manufacturing a semiconductor structure includes forming a trench in a dielectric structure; forming a spacer layer on a lateral surface of the dielectric structure exposed by the trench; after forming the spacer layer, forming a first electrically conductive feature in the trench; removing at least portion of the dielectric structure to form a recess; forming an etch stop layer in the recess and over the first electrically conductive feature; and after forming the etch stop layer, depositing a dielectric layer in the recess and over the first electrically conductive feature.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: November 28, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chieh-Han Wu, Hwei-Jay Chu, An-Dih Yu, Tzu-Hui Wei, Cheng-Hsiung Tsai, Chung-Ju Lee, Shin-Yi Yang, Ming-Han Lee
  • Publication number: 20230378255
    Abstract: A method for manufacturing a semiconductor structure includes forming a trench in a dielectric structure; forming a spacer layer on a lateral surface of the dielectric structure exposed by the trench; after forming the spacer layer, forming a first electrically conductive feature in the trench; removing at least portion of the dielectric structure to form a recess; forming an etch stop layer in the recess and over the first electrically conductive feature; and after forming the etch stop layer, depositing a dielectric layer in the recess and over the first electrically conductive feature.
    Type: Application
    Filed: August 2, 2023
    Publication date: November 23, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chieh-Han WU, Hwei-Jay CHU, An-Dih YU, Tzu-Hui WEI, Cheng-Hsiung TSAI, Chung-Ju LEE, Shin-Yi YANG, Ming-Han LEE
  • Publication number: 20230253312
    Abstract: Interconnect structures and methods of forming the same are provided. An interconnect structure according to the present disclosure includes a conductive line feature over a substrate, a conductive etch stop layer over the conductive line feature, a contact via over the conductive etch stop layer, and a barrier layer disposed along a sidewall of the conductive line feature, a sidewall of the conductive etch stop layer, and a sidewall of the contact via.
    Type: Application
    Filed: April 17, 2023
    Publication date: August 10, 2023
    Inventors: Chieh-Han Wu, Cheng-Hsiung Tsai, Chih Wei Lu, Chung-Ju Lee
  • Patent number: 11676862
    Abstract: An interconnection structure, along with methods of forming such, are described. The structure includes a first conductive feature having a first thickness, a first dielectric material disposed adjacent the first conductive feature, and the first dielectric material has a second thickness greater than the first thickness. The structure further includes a second conductive feature disposed adjacent the first dielectric material, a first etch stop layer disposed on the first conductive feature, a second etch stop layer disposed on the first dielectric material, and a second dielectric material disposed on the first etch stop layer and the second etch stop layer. The second dielectric material is in contact with the first dielectric material.
    Type: Grant
    Filed: February 26, 2021
    Date of Patent: June 13, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hwei-Jay Chu, Chieh-Han Wu, Hsin-Chieh Yao, Cheng-Hsiung Tsai, Chung-Ju Lee
  • Patent number: 11631639
    Abstract: Interconnect structures and methods of forming the same are provided. An interconnect structure according to the present disclosure includes a conductive line feature over a substrate, a conductive etch stop layer over the conductive line feature, a contact via over the conductive etch stop layer, and a barrier layer disposed along a sidewall of the conductive line feature, a sidewall of the conductive etch stop layer, and a sidewall of the contact via.
    Type: Grant
    Filed: February 14, 2022
    Date of Patent: April 18, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chieh-Han Wu, Cheng-Hsiung Tsai, Chih Wei Lu, Chung-Ju Lee
  • Publication number: 20230062825
    Abstract: A semiconductor structure includes a first metallization feature, a first dielectric structure over the first metallization feature, a second metallization feature embedded in the first dielectric structure, a via structure between the first metallization feature and the second metallization feature, and a first insulating layer between the first dielectric structure and the first metallization feature, and between the first dielectric structure and the via structure. The first metallization feature extends along a first direction, and the second metallization feature extends along a second direction different from the first direction. The first insulating layer covers first sidewalls of the via structure along the second direction.
    Type: Application
    Filed: August 30, 2021
    Publication date: March 2, 2023
    Inventors: HWEI-JAY CHU, CHIEH-HAN WU, CHENG-HSIUNG TSAI, CHUNG-JU LEE
  • Publication number: 20230062416
    Abstract: A method for manufacturing a semiconductor structure includes forming a trench in a dielectric structure; forming a spacer layer on a lateral surface of the dielectric structure exposed by the trench; after forming the spacer layer, forming a first electrically conductive feature in the trench; removing at least portion of the dielectric structure to form a recess; forming an etch stop layer in the recess and over the first electrically conductive feature; and after forming the etch stop layer, depositing a dielectric layer in the recess and over the first electrically conductive feature.
    Type: Application
    Filed: August 30, 2021
    Publication date: March 2, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chieh-Han WU, Hwei-Jay CHU, An-Dih YU, Tzu-Hui WEI, Cheng-Hsiung TSAI, Chung-Ju LEE, Shin-Yi YANG, Ming-Han LEE
  • Publication number: 20230039661
    Abstract: An interconnect structure and methods of forming the same are described. In some embodiments, the structure includes a dielectric layer, a first conductive feature disposed in the dielectric layer, and a second conductive feature disposed over the first conductive feature. The second conductive feature includes a first sidewall, a first bottom, and a first angle between the first sidewall and the first bottom. The structure further includes a third conductive feature disposed over the dielectric layer and adjacent the second conductive feature. The third conductive feature includes a second sidewall, a second bottom, and a second angle between the second sidewall and the second bottom, the second angle is substantially different from the first angle, and the second and third conductive features are partially overlapping in an axis substantially parallel to a major surface of the substrate.
    Type: Application
    Filed: March 15, 2022
    Publication date: February 9, 2023
    Inventors: Hwei-Jay CHU, Chieh-Han WU, Hsin-Chieh YAO, Wei-Hao LIAO, Yu-Teng DAI, Hsi-Wen TIEN, Chih Wei LU
  • Publication number: 20220277995
    Abstract: An interconnection structure, along with methods of forming such, are described. The structure includes a first conductive feature having a first thickness, a first dielectric material disposed adjacent the first conductive feature, and the first dielectric material has a second thickness greater than the first thickness. The structure further includes a second conductive feature disposed adjacent the first dielectric material, a first etch stop layer disposed on the first conductive feature, a second etch stop layer disposed on the first dielectric material, and a second dielectric material disposed on the first etch stop layer and the second etch stop layer. The second dielectric material is in contact with the first dielectric material.
    Type: Application
    Filed: February 26, 2021
    Publication date: September 1, 2022
    Inventors: Hwei-Jay CHU, Chieh-Han WU, Hsin-Chieh YAO, Cheng-Hsiung TSAI, Chung-Ju LEE
  • Patent number: 11393718
    Abstract: A method for forming a semiconductor structure includes forming a first cap layer over a metal layer. The method also includes patterning the metal layer and the first cap layer to form openings exposing the gate structure, and forming a first dielectric layer in the openings, and patterning the first cap layer to form a via cap plug over the metal layer. The method also includes forming a second dielectric layer over the via cap plug and the metal layer, and forming a trench in the second dielectric material to expose the via cap plug. The method also includes removing the via cap plug to enlarge the trench and filling the trench with a conductive material.
    Type: Grant
    Filed: July 30, 2020
    Date of Patent: July 19, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hwei-Jay Chu, Chieh-Han Wu, Cheng-Hsiung Tsai, Chih-Wei Lu, Chung-Ju Lee
  • Publication number: 20220165661
    Abstract: Interconnect structures and methods of forming the same are provided. An interconnect structure according to the present disclosure includes a conductive line feature over a substrate, a conductive etch stop layer over the conductive line feature, a contact via over the conductive etch stop layer, and a barrier layer disposed along a sidewall of the conductive line feature, a sidewall of the conductive etch stop layer, and a sidewall of the contact via.
    Type: Application
    Filed: February 14, 2022
    Publication date: May 26, 2022
    Inventors: Chieh-Han Wu, Cheng-Hsiung Tsai, Chih Wei Lu, Chung-Ju Lee
  • Patent number: 11251118
    Abstract: Interconnect structures and methods of forming the same are provided. An interconnect structure according to the present disclosure includes a conductive line feature over a substrate, a conductive etch stop layer over the conductive line feature, a contact via over the conductive etch stop layer, and a barrier layer disposed along a sidewall of the conductive line feature, a sidewall of the conductive etch stop layer, and a sidewall of the contact via.
    Type: Grant
    Filed: September 17, 2019
    Date of Patent: February 15, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chieh-Han Wu, Cheng-Hsiung Tsai, Chih Wei Lu, Chung-Ju Lee
  • Publication number: 20210242078
    Abstract: A method for forming a semiconductor structure includes forming a first cap layer over a metal layer. The method also includes patterning the metal layer and the first cap layer to form openings exposing the gate structure, and forming a first dielectric layer in the openings, and patterning the first cap layer to form a via cap plug over the metal layer. The method also includes forming a second dielectric layer over the via cap plug and the metal layer, and forming a trench in the second dielectric material to expose the via cap plug. The method also includes removing the via cap plug to enlarge the trench and filling the trench with a conductive material.
    Type: Application
    Filed: July 30, 2020
    Publication date: August 5, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hwei-Jay CHU, Chieh-Han WU, Cheng-Hsiung TSAI, Chih-Wei LU, Chung-Ju LEE