Patents by Inventor Chieh-Han Wu
Chieh-Han Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240021472Abstract: An interconnection structure, along with methods of forming such, are described. The structure includes a first conductive feature having a first thickness, a first dielectric material disposed adjacent the first conductive feature, and the first dielectric material has a second thickness greater than the first thickness. The structure further includes a second conductive feature disposed adjacent the first dielectric material, a first etch stop layer disposed on the first conductive feature, a second etch stop layer disposed on the first dielectric material, and a second dielectric material disposed on the first etch stop layer and the second etch stop layer. The second dielectric material is in contact with the first dielectric material.Type: ApplicationFiled: May 28, 2023Publication date: January 18, 2024Inventors: Hwei-Jay CHU, Chieh-Han WU, Hsin-Chieh YAO, Cheng-Hsiung TSAI, Chung-Ju LEE
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Patent number: 11830910Abstract: A method for manufacturing a semiconductor structure includes forming a trench in a dielectric structure; forming a spacer layer on a lateral surface of the dielectric structure exposed by the trench; after forming the spacer layer, forming a first electrically conductive feature in the trench; removing at least portion of the dielectric structure to form a recess; forming an etch stop layer in the recess and over the first electrically conductive feature; and after forming the etch stop layer, depositing a dielectric layer in the recess and over the first electrically conductive feature.Type: GrantFiled: August 30, 2021Date of Patent: November 28, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chieh-Han Wu, Hwei-Jay Chu, An-Dih Yu, Tzu-Hui Wei, Cheng-Hsiung Tsai, Chung-Ju Lee, Shin-Yi Yang, Ming-Han Lee
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Publication number: 20230378255Abstract: A method for manufacturing a semiconductor structure includes forming a trench in a dielectric structure; forming a spacer layer on a lateral surface of the dielectric structure exposed by the trench; after forming the spacer layer, forming a first electrically conductive feature in the trench; removing at least portion of the dielectric structure to form a recess; forming an etch stop layer in the recess and over the first electrically conductive feature; and after forming the etch stop layer, depositing a dielectric layer in the recess and over the first electrically conductive feature.Type: ApplicationFiled: August 2, 2023Publication date: November 23, 2023Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chieh-Han WU, Hwei-Jay CHU, An-Dih YU, Tzu-Hui WEI, Cheng-Hsiung TSAI, Chung-Ju LEE, Shin-Yi YANG, Ming-Han LEE
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Publication number: 20230253312Abstract: Interconnect structures and methods of forming the same are provided. An interconnect structure according to the present disclosure includes a conductive line feature over a substrate, a conductive etch stop layer over the conductive line feature, a contact via over the conductive etch stop layer, and a barrier layer disposed along a sidewall of the conductive line feature, a sidewall of the conductive etch stop layer, and a sidewall of the contact via.Type: ApplicationFiled: April 17, 2023Publication date: August 10, 2023Inventors: Chieh-Han Wu, Cheng-Hsiung Tsai, Chih Wei Lu, Chung-Ju Lee
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Patent number: 11676862Abstract: An interconnection structure, along with methods of forming such, are described. The structure includes a first conductive feature having a first thickness, a first dielectric material disposed adjacent the first conductive feature, and the first dielectric material has a second thickness greater than the first thickness. The structure further includes a second conductive feature disposed adjacent the first dielectric material, a first etch stop layer disposed on the first conductive feature, a second etch stop layer disposed on the first dielectric material, and a second dielectric material disposed on the first etch stop layer and the second etch stop layer. The second dielectric material is in contact with the first dielectric material.Type: GrantFiled: February 26, 2021Date of Patent: June 13, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hwei-Jay Chu, Chieh-Han Wu, Hsin-Chieh Yao, Cheng-Hsiung Tsai, Chung-Ju Lee
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Patent number: 11631639Abstract: Interconnect structures and methods of forming the same are provided. An interconnect structure according to the present disclosure includes a conductive line feature over a substrate, a conductive etch stop layer over the conductive line feature, a contact via over the conductive etch stop layer, and a barrier layer disposed along a sidewall of the conductive line feature, a sidewall of the conductive etch stop layer, and a sidewall of the contact via.Type: GrantFiled: February 14, 2022Date of Patent: April 18, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chieh-Han Wu, Cheng-Hsiung Tsai, Chih Wei Lu, Chung-Ju Lee
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Publication number: 20230062416Abstract: A method for manufacturing a semiconductor structure includes forming a trench in a dielectric structure; forming a spacer layer on a lateral surface of the dielectric structure exposed by the trench; after forming the spacer layer, forming a first electrically conductive feature in the trench; removing at least portion of the dielectric structure to form a recess; forming an etch stop layer in the recess and over the first electrically conductive feature; and after forming the etch stop layer, depositing a dielectric layer in the recess and over the first electrically conductive feature.Type: ApplicationFiled: August 30, 2021Publication date: March 2, 2023Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chieh-Han WU, Hwei-Jay CHU, An-Dih YU, Tzu-Hui WEI, Cheng-Hsiung TSAI, Chung-Ju LEE, Shin-Yi YANG, Ming-Han LEE
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Publication number: 20230062825Abstract: A semiconductor structure includes a first metallization feature, a first dielectric structure over the first metallization feature, a second metallization feature embedded in the first dielectric structure, a via structure between the first metallization feature and the second metallization feature, and a first insulating layer between the first dielectric structure and the first metallization feature, and between the first dielectric structure and the via structure. The first metallization feature extends along a first direction, and the second metallization feature extends along a second direction different from the first direction. The first insulating layer covers first sidewalls of the via structure along the second direction.Type: ApplicationFiled: August 30, 2021Publication date: March 2, 2023Inventors: HWEI-JAY CHU, CHIEH-HAN WU, CHENG-HSIUNG TSAI, CHUNG-JU LEE
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Publication number: 20230039661Abstract: An interconnect structure and methods of forming the same are described. In some embodiments, the structure includes a dielectric layer, a first conductive feature disposed in the dielectric layer, and a second conductive feature disposed over the first conductive feature. The second conductive feature includes a first sidewall, a first bottom, and a first angle between the first sidewall and the first bottom. The structure further includes a third conductive feature disposed over the dielectric layer and adjacent the second conductive feature. The third conductive feature includes a second sidewall, a second bottom, and a second angle between the second sidewall and the second bottom, the second angle is substantially different from the first angle, and the second and third conductive features are partially overlapping in an axis substantially parallel to a major surface of the substrate.Type: ApplicationFiled: March 15, 2022Publication date: February 9, 2023Inventors: Hwei-Jay CHU, Chieh-Han WU, Hsin-Chieh YAO, Wei-Hao LIAO, Yu-Teng DAI, Hsi-Wen TIEN, Chih Wei LU
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Publication number: 20220277995Abstract: An interconnection structure, along with methods of forming such, are described. The structure includes a first conductive feature having a first thickness, a first dielectric material disposed adjacent the first conductive feature, and the first dielectric material has a second thickness greater than the first thickness. The structure further includes a second conductive feature disposed adjacent the first dielectric material, a first etch stop layer disposed on the first conductive feature, a second etch stop layer disposed on the first dielectric material, and a second dielectric material disposed on the first etch stop layer and the second etch stop layer. The second dielectric material is in contact with the first dielectric material.Type: ApplicationFiled: February 26, 2021Publication date: September 1, 2022Inventors: Hwei-Jay CHU, Chieh-Han WU, Hsin-Chieh YAO, Cheng-Hsiung TSAI, Chung-Ju LEE
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Patent number: 11393718Abstract: A method for forming a semiconductor structure includes forming a first cap layer over a metal layer. The method also includes patterning the metal layer and the first cap layer to form openings exposing the gate structure, and forming a first dielectric layer in the openings, and patterning the first cap layer to form a via cap plug over the metal layer. The method also includes forming a second dielectric layer over the via cap plug and the metal layer, and forming a trench in the second dielectric material to expose the via cap plug. The method also includes removing the via cap plug to enlarge the trench and filling the trench with a conductive material.Type: GrantFiled: July 30, 2020Date of Patent: July 19, 2022Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hwei-Jay Chu, Chieh-Han Wu, Cheng-Hsiung Tsai, Chih-Wei Lu, Chung-Ju Lee
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Publication number: 20220165661Abstract: Interconnect structures and methods of forming the same are provided. An interconnect structure according to the present disclosure includes a conductive line feature over a substrate, a conductive etch stop layer over the conductive line feature, a contact via over the conductive etch stop layer, and a barrier layer disposed along a sidewall of the conductive line feature, a sidewall of the conductive etch stop layer, and a sidewall of the contact via.Type: ApplicationFiled: February 14, 2022Publication date: May 26, 2022Inventors: Chieh-Han Wu, Cheng-Hsiung Tsai, Chih Wei Lu, Chung-Ju Lee
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Patent number: 11251118Abstract: Interconnect structures and methods of forming the same are provided. An interconnect structure according to the present disclosure includes a conductive line feature over a substrate, a conductive etch stop layer over the conductive line feature, a contact via over the conductive etch stop layer, and a barrier layer disposed along a sidewall of the conductive line feature, a sidewall of the conductive etch stop layer, and a sidewall of the contact via.Type: GrantFiled: September 17, 2019Date of Patent: February 15, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chieh-Han Wu, Cheng-Hsiung Tsai, Chih Wei Lu, Chung-Ju Lee
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Publication number: 20210242078Abstract: A method for forming a semiconductor structure includes forming a first cap layer over a metal layer. The method also includes patterning the metal layer and the first cap layer to form openings exposing the gate structure, and forming a first dielectric layer in the openings, and patterning the first cap layer to form a via cap plug over the metal layer. The method also includes forming a second dielectric layer over the via cap plug and the metal layer, and forming a trench in the second dielectric material to expose the via cap plug. The method also includes removing the via cap plug to enlarge the trench and filling the trench with a conductive material.Type: ApplicationFiled: July 30, 2020Publication date: August 5, 2021Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hwei-Jay CHU, Chieh-Han WU, Cheng-Hsiung TSAI, Chih-Wei LU, Chung-Ju LEE
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Publication number: 20210082804Abstract: Interconnect structures and methods of forming the same are provided. An interconnect structure according to the present disclosure includes a conductive line feature over a substrate, a conductive etch stop layer over the conductive line feature, a contact via over the conductive etch stop layer, and a barrier layer disposed along a sidewall of the conductive line feature, a sidewall of the conductive etch stop layer, and a sidewall of the contact via.Type: ApplicationFiled: September 17, 2019Publication date: March 18, 2021Inventors: Chieh-Han Wu, Cheng-Hsiung Tsai, Chih Wei Lu, Chung-Ju Lee
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Patent number: 10049919Abstract: A method of forming a target pattern includes forming a plurality of lines over a substrate with a first mask and forming a first spacer layer over the substrate, over the plurality of lines, and onto sidewalls of the plurality of lines. The plurality of lines is removed, thereby providing a patterned first spacer layer over the substrate. The method further includes forming a second spacer layer over the substrate, over the patterned first spacer layer, and onto sidewalls of the patterned first spacer layer, and forming a patterned material layer over the second spacer layer with a second mask. Whereby, the patterned material layer and the second spacer layer collectively define a plurality of trenches.Type: GrantFiled: February 17, 2017Date of Patent: August 14, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chieh-Han Wu, Cheng-Hsiung Tsai, Chung-Ju Lee, Ming-Feng Shieh, Ru-Gun Liu, Shau-Lin Shue, Tien-I Bao
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Publication number: 20170162435Abstract: A method of forming a target pattern includes forming a plurality of lines over a substrate with a first mask and forming a first spacer layer over the substrate, over the plurality of lines, and onto sidewalls of the plurality of lines. The plurality of lines is removed, thereby providing a patterned first spacer layer over the substrate. The method further includes forming a second spacer layer over the substrate, over the patterned first spacer layer, and onto sidewalls of the patterned first spacer layer, and forming a patterned material layer over the second spacer layer with a second mask. Whereby, the patterned material layer and the second spacer layer collectively define a plurality of trenches.Type: ApplicationFiled: February 17, 2017Publication date: June 8, 2017Inventors: Chieh-Han WU, Cheng-Hsiung TSAI, Chung-Ju LEE, Ming-Feng SHIEH, Ru-Gun LIU, Shau-Lin SHUE, Tien-I BAO
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Patent number: 9653349Abstract: A method of fabricating a semiconductor integrated circuit (IC) is disclosed. A substrate having a dielectric layer over it is provided. A block co-polymer (BCP) layer is deposited over the dielectric layer. The BCP layer is then annealed to form a first polymer nanostructures surrounded by a second polymer nanostructures over the dielectric layer. The second polymer nanostructure is selectively etched using the first polymer nanostructure as an etch mask to form a nano-block. The dielectric layer is selectively etched using the nano-block as an etch mask to form a nano-trench. The nano-trenched is sealed to form a nano-air-gap.Type: GrantFiled: January 24, 2014Date of Patent: May 16, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Cheng-Hsiung Tsai, Chieh-Han Wu, Chung-Ju Lee, Shau-Lin Shue
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Patent number: 9640397Abstract: A method of fabricating a semiconductor integrated circuit (IC) is disclosed. A first layer is deposited over a substrate. A plurality of mandrels is formed over the first layer. Guiding-spacers are formed along sidewalls of the mandrels. Then the mandrels are removed. A neutral layer (NL) and a block copolymer (BCP) layer are deposited over the first layer and the guiding-spacers. A anneal is applied to the BCP layer to form a first polymer nanostructure between the guiding-spacers and being surrounded by a second polymer nanostructure. The first polymer nanostructures locate at a same distance from the first layer. Polymer nano-blocks are formed by selectively etching the second polymer nanostructure and the NL. By using the polymer nano-blocks and the guiding spacer as etch masks, the first layer is etched to form openings. The substrate is etched through the openings to form substrate trench and substrate fin.Type: GrantFiled: March 14, 2014Date of Patent: May 2, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chieh-Han Wu, Chung-Ju Lee, Tien-I Bao, Tsung-Yu Chen, Shinn-Sheng Yu, Yu-Fu Lin, Jeng-Horng Chen
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Patent number: 9576814Abstract: A method of forming a target pattern includes forming a plurality of lines over a substrate with a first mask and forming a first spacer layer over the substrate, over the plurality of lines, and onto sidewalls of the plurality of lines. The plurality of lines is removed, thereby providing a patterned first spacer layer over the substrate. The method further includes forming a second spacer layer over the substrate, over the patterned first spacer layer, and onto sidewalls of the patterned first spacer layer, and forming a patterned material layer over the second spacer layer with a second mask. Whereby, the patterned material layer and the second spacer layer collectively define a plurality of trenches.Type: GrantFiled: September 14, 2015Date of Patent: February 21, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chieh-Han Wu, Cheng-Hsiung Tsai, Chung-Ju Lee, Ming-Feng Shieh, Ru-Gun Liu, Shau-Lin Shue, Tien-I Bao