Patents by Inventor Chieh Hsien Quek

Chieh Hsien Quek has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230290721
    Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Individual of the conductive tiers comprise laterally-outer edges comprising conductive molybdenum-containing metal material extending horizontally-along its memory block. Channel-material strings extend through the insulative tiers and the conductive tiers. At least one of conductive or semiconductive material is formed extending horizontally-along the memory blocks laterally-outward of the laterally-outer edges comprising the conductive molybdenum-containing metal material that extends horizontally-along its memory block. Insulator material extending horizontally-along the memory blocks is formed laterally-outward of the at least one of the conductive or the semiconductive material that is laterally-outward of the laterally-outer edges comprising the conductive molybdenum-containing metal material.
    Type: Application
    Filed: March 8, 2022
    Publication date: September 14, 2023
    Applicant: Micron Technology, Inc.
    Inventors: Jordan D. Greenlee, Jiewei Chen, Sijia Yu, Chieh Hsien Quek, Rita J. Klein, Nancy M. Lomeli
  • Patent number: 11742282
    Abstract: Some embodiments include conductive interconnects which include the first and second conductive materials, and which extend upwardly from a conductive structure. Some embodiments include integrated assemblies having conductive interconnects.
    Type: Grant
    Filed: August 7, 2020
    Date of Patent: August 29, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Jordan D. Greenlee, Rita J. Klein, Everett A. McTeer, John D. Hopkins, Shuangqiang Luo, Song Kai Tan, Jing Wai Fong, Anurag Jindal, Chieh Hsien Quek
  • Publication number: 20220044999
    Abstract: Some embodiments include conductive interconnects which include the first and second conductive materials, and which extend upwardly from a conductive structure. Some embodiments include integrated assemblies having conductive interconnects.
    Type: Application
    Filed: August 7, 2020
    Publication date: February 10, 2022
    Applicant: Micron Technology, Inc.
    Inventors: Jordan D. Greenlee, Rita J. Klein, Everett A. McTeer, John D. Hopkins, Shuangqiang Luo, Song Kai Tan, Jing Wai Fong, Anurag Jindal, Chieh Hsien Quek
  • Publication number: 20220045007
    Abstract: Methods for forming microelectronic devices include forming a staircase structure in a stack structure having a vertically alternating sequence of insulative and conductive materials arranged in tiers. Steps are at lateral ends of the tiers. Contact openings of different aspect ratios are formed in fill material adjacent the staircase structure, with some openings terminating in the fill material and others exposing portions of the conductive material of upper tiers of the stack structure. Additional conductive material is selectively formed on the exposed portions of the conductive material. The contact openings initially terminating in the fill material are extended to expose portions of the conductive material of lower elevations. Contacts are formed, with some extending to the additional conductive material and others extending to conductive material of the tiers of the lower elevations. Microelectronic devices and systems incorporating such staircase structures and contacts are also disclosed.
    Type: Application
    Filed: October 25, 2021
    Publication date: February 10, 2022
    Inventors: Biow Hiem Ong, David A. Daycock, Chieh Hsien Quek, Chii Wean Calvin Chen, Christian George Emor, Wing Yu Lo
  • Patent number: 11158577
    Abstract: Methods for forming microelectronic devices include forming a staircase structure in a stack structure having a vertically alternating sequence of insulative and conductive materials arranged in tiers. Steps are at lateral ends of the tiers. Contact openings of different aspect ratios are formed in fill material adjacent the staircase structure, with some openings terminating in the fill material and others exposing portions of the conductive material of upper tiers of the stack structure. Additional conductive material is selectively formed on the exposed portions of the conductive material. The contact openings initially terminating in the fill material are extended to expose portions of the conductive material of lower elevations. Contacts are formed, with some extending to the additional conductive material and others extending to conductive material of the tiers of the lower elevations. Microelectronic devices and systems incorporating such staircase structures and contacts are also disclosed.
    Type: Grant
    Filed: January 31, 2020
    Date of Patent: October 26, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Biow Hiem Ong, David A. Daycock, Chieh Hsien Quek, Chii Wean Calvin Chen, Christian George Emor, Wing Yu Lo
  • Publication number: 20210242131
    Abstract: Methods for forming microelectronic devices include forming a staircase structure in a stack structure having a vertically alternating sequence of insulative and conductive materials arranged in tiers. Steps are at lateral ends of the tiers. Contact openings of different aspect ratios are formed in fill material adjacent the staircase structure, with some openings terminating in the fill material and others exposing portions of the conductive material of upper tiers of the stack structure. Additional conductive material is selectively formed on the exposed portions of the conductive material. The contact openings initially terminating in the fill material are extended to expose portions of the conductive material of lower elevations. Contacts are formed, with some extending to the additional conductive material and others extending to conductive material of the tiers of the lower elevations. Microelectronic devices and systems incorporating such staircase structures and contacts are also disclosed.
    Type: Application
    Filed: January 31, 2020
    Publication date: August 5, 2021
    Inventors: Biow Hiem Ong, David A. Daycock, Chieh Hsien Quek, Chii Wean Calvin Chen, Christian George Emor, Wing Yu Lo