Abstract: An electronic device casing includes a main casing and a flexible member. The main casing includes a first surface and a second surface opposite to each other, an opening passing through the first surface and the second surface, and a fixing member located near the opening and protruding from the second surface. The flexible member and the main casing are integrally formed by double injection molding. The flexible member is disposed on the second surface and covers the opening. The fixing member passes through the flexible member. A manufacturing method of electronic device casing is further provided.

Abstract: A multi-channel decoding method includes: receiving an input signal to generate a channel output signal; providing a first test signal serving as the input signal in a first calibration mode; and adjusting a DC voltage level of the channel output signal with a first calibration signal by reducing a difference between a first predetermined reference signal level and a DC voltage level of the channel output signal generated from the first test signal.

Abstract: A FM receiver comprises an IF filter, a demodulator and a decoder. The IF filter generates an RSSI and a FM modulated signal in response to a FM signal. The demodulator comprises a duty-to-voltage amplifier for amplifying a peak of a MPX signal. The duty-to-voltage amplifier comprises a current source, a switch and a current splitter. The current source generates a current. The switch controls a flow of the first current in response to a PWM signal. The current splitter splits the flow of the current into a sub-flow in response to the RSSI. The peak of the MPX signal is proportional to the sub-flow. The decoder receives the MPX signal to generate an audio signal to play sound.

Abstract: A multi-channel decoding method includes: receiving an input signal to generate a channel output signal; providing a first test signal serving as the input signal in a first calibration mode; and adjusting a DC voltage level of the channel output signal with a first calibration signal by reducing a difference between a first predetermined reference signal level and a DC voltage level of the channel output signal generated from the first test signal.

Abstract: An FM receiver and a pilot detector thereof, and a method for determining a type of a processed signal are provided. The FM receiver comprises a demodulator, a band pass filter (BPF), and a pilot detector. The demodulator generates a multiplexed (MPX) signal. The BPF filters the MPX signal to generate a pilot signal. The pilot detector comprises a signal addition device and a comparator. The signal addition device adds the processed signal for a period of time and to generate a result signal in response to the addition. The comparator compares the result signal with a reference to determine whether the type is stereo. The method comprises the steps of: adding the processed signal for a period of time; generating a result signal in response to the addition; and comparing the result signal with a reference to determine whether the type is stereo.

Abstract: A multi-channel decoding method includes: receiving an input signal to generate a first channel output signal and a second channel output signal, wherein the input signal is mixed with a specific clock signal; and gradually changing an amplitude of the specific clock signal from a first value to a second value when switching from a first mode corresponding to a first number of channels to a second mode corresponding to a second number of channels. Systems utilizing the method and another method further comprising calibration are also disclosed.

Abstract: A stereo decoder and a method therefor are provided. The stereo decoder receives a MPX signal from an FM demodulator, and comprises a first auto-calibration circuit, a band-pass filter, a second auto-calibration circuit, a slicer and a PLL circuit. The first auto-calibration circuit generates a first control signal. The band-pass filter generates the pilot signal by filtering the MPX signal with a center frequency set by the first control signal. The second auto-calibration circuit generates a second control signal. The slicer converts the pilot signal into a square wave signal. The PLL circuit comprises a voltage controlled oscillator for generating an oscillation frequency in response to the second control signal. The PLL circuit receives the square wave signal to generate the reference signal around the predetermined frequency in response to the oscillation frequency.

Abstract: A calibration circuit for calibrating an output level of a demodulator includes a test signal generator, an RSSI module and a calibration module. The test signal generator generates a test signal, and the RSSI module detects the test signal to generate a control signal, wherein the control signal controls the demodulator to process the test signal to generate a determined output signal. The calibration module then calibrates the RSSI module according to the output signal in order to calibrate the output level of the demodulator. When the control signal is utilized to selectively enable or disable a soft-mute function of the demodulator, the calibration module can be utilized to calibrate or determine the soft-mute function of the demodulator.

Abstract: A stereo decoding system comprises an oscillator, a bandpass filter, a PLL unit and a stereo decoder. The oscillator generates a first signal with a center frequency. The bandpass filter receives a stereo multiplexed signal and the first signal to filter out a pilot signal. The PLL unit receives the pilot signal to generate a PLL output signal. The stereo decoder receives the stereo multiplexed signal and the PLL output signal to separate a left channel signal and a right channel signal from the stereo multiplexed signal.

Abstract: A FM receiver comprises an IF filter, a demodulator and a decoder. The IF filter generates an RSSI and a FM modulated signal in response to a FM signal. The demodulator comprises a duty-to-voltage amplifier for amplifying a peak of a MPX signal. The duty-to-voltage amplifier comprises a current source, a switch and a current splitter. The current source generates a current. The switch controls a flow of the first current in response to a PWM signal. The current splitter splits the flow of the current into a sub-flow in response to the RSSI. The peak of the MPX signal is proportional to the sub-flow. The decoder receives the MPX signal to generate an audio signal to play sound.

Abstract: A multi-channel decoding method includes: receiving an input signal to generate a first channel output signal and a second channel output signal, wherein the input signal is mixed with a specific clock signal; and gradually changing an amplitude of the specific clock signal from a first value to a second value when switching from a first mode corresponding to a first number of channels to a second mode corresponding to a second number of channels. Systems utilizing the method and another method further comprising calibration are also disclosed.

Abstract: A multi-channel blend system includes a calibration circuit and a decoding circuit having a gain amplifying module. The decoding circuit is utilized for receiving an input signal to generate a first channel output signal and a second channel output signal. The gain amplifying module is utilized for providing a gain value for determining a separation ratio between the first channel output signal and the second channel output signal according to a calibration signal. The calibration circuit is utilized for providing a predetermined test signal serving as the input signal so as to generate the calibration signal according to at least one of the first and second channel output signals generated from the predetermined test signal.

Abstract: A calibration circuit for calibrating an output level of a demodulator includes a test signal generator, an RSSI module and a calibration module. The test signal generator generates a test signal, and the RSSI module detects the test signal to generate a control signal, wherein the control signal controls the demodulator to process the test signal to generate a determined output signal. The calibration module then calibrates the RSSI module according to the output signal in order to calibrate the output level of the demodulator. When the control signal is utilized to selectively enable or disable a soft-mute function of the demodulator, the calibration module can be utilized to calibrate or determine the soft-mute function of the demodulator.

Abstract: A FM receiver comprises an IF filter, a demodulator and a decoder. The IF filter generates an RSSI and a FM modulated signal in response to a FM signal. The demodulator comprises a duty-to-voltage amplifier for amplifying a peak of a MPX signal. The duty-to-voltage amplifier comprises a current source, a switch and a current splitter. The current source generates a current. The switch controls a flow of the first current in response to a PWM signal. The current splitter splits the flow of the current into a sub-flow in response to the RSSI. The peak of the MPX signal is proportional to the sub-flow. The decoder receives the MPX signal to generate an audio signal to play sound.

Abstract: A stereo decoding system comprises an oscillator, a bandpass filter, a PLL unit and a stereo decoder. The oscillator generates a first signal with a center frequency. The bandpass filter receives a stereo multiplexed signal and the first signal to filter out a pilot signal. The PLL unit receives the pilot signal to generate a PLL output signal. The stereo decoder receives the stereo multiplexed signal and the PLL output signal to separate a left channel signal and a right channel signal from the stereo multiplexed signal.

Abstract: The present invention discloses an on-line calibration method, which utilizes two calibration algorithms running in the background without interrupting the normal operation of the analog signal process. The method includes performing a residue amplifier gain error calibration and performing a DAC non-linearity calibration. The residue amplifier gain error calibration can reduce the gain error of the residue amplifier for a missing code or a missing decision level phenomenon. The DAC non-linearity calibration can relax the matching requirement of passive components in current semiconductor processes. The present invention discloses a two-step ADC (Analog-to-Digital Converter), which includes a first signal processing unit, a second signal processing unit, a programmable gain control unit and a programmable reference voltage generator, performing the on-line calibration method.

Abstract: The present invention discloses an on-line calibration method, which utilizes two calibration algorithms running in the background without interrupting the normal operation of the analog signal process. The method includes performing a residue amplifier gain error calibration and performing a DAC non-linearity calibration. The residue amplifier gain error calibration can reduce the gain error of the residue amplifier for a missing code or a missing decision level phenomenon. The DAC non-linearity calibration can relax the matching requirement of passive components in current semiconductor processes. The present invention discloses a two-step ADC (Analog-to-Digital Converter), which includes a first signal processing unit, a second signal processing unit, a programmable gain control unit and a programmable reference voltage generator, performing the on-line calibration method.

Abstract: A digital-to-analog converter (DAC) for use in high-speed wireless communications. The DAC of the invention comprises a plurality of current steering cells to bi-directionally provide a differential current output. When the DAC sets the differential current output to zero for example, each of the current steering cells establishes dummy branches between a pair of current sources and thereby prevents the current sources from floating. This in turn enables the DAC to operate with a higher update rate.

Abstract: The subject invention relates to a type of multi-bits successive-approximation ADC to convert analog signals into a N-bits digital output code, wherein N is the number of bits of output code. The ADC includes (a) an input sample/hold circuit that takes the sample of analog input signals during the first half of clock cycle, and maintains the analog input signals after the sampling and during a conversion process. The ADC also includes (b) a reference voltage generator, to produce different reference voltages, (c) CLOCK pulse generation circuitry to continuously produce CLOCK pulse signals, (d) several comparators for comparison of the sampled input signals with a rough reference voltage to produce a rough digital output code. The ADC applies a temperature scale to roughly estimate the sampled analog input signals, this to be completed in a second half of the CLOCK cycle.