Patents by Inventor Chieh-Ju Chang

Chieh-Ju Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6812148
    Abstract: Embodiments of the present invention relate to a method for preventing gate oxide thinning in a recess LOCOS process. The plurality of trenches are separated by a patterned pad oxide and a patterned silicon nitride layer The patterned silicon nitride layer and the patterned pad oxide layer are removed to expose a surface of the substrate as an active area of the semiconductor device. An ion drive-in to the active area on the substrate is performed by directing a flow of oxygen and nitrogen toward the substrate at a predetermined temperature and with a sufficient amount of oxygen to at least substantially prevent silicon nitride from forming on the field oxide regions. The method further comprises forming a sacrificial oxide layer on the active area, removing the sacrificial oxide layer to expose the active area, and forming a gate oxide layer on the active area.
    Type: Grant
    Filed: August 13, 2002
    Date of Patent: November 2, 2004
    Assignee: Mosel Vitelic, Inc.
    Inventors: Chieh-Ju Chang, Tsai-Sen Lin, Chon-Shin Jou, Yifu Chung
  • Publication number: 20040031772
    Abstract: Embodiments of the present invention relate to a method for preventing gate oxide thinning in a recess LOCOS process. A method of forming a gate oxide on a substrate comprises providing a substrate having thereon a plurality of trenches having gate oxides formed therein, wherein the plurality of trenches are separated by a patterned pad oxide and a patterned silicon nitride layer disposed thereon and used to form the plurality of trenches. The patterned silicon nitride layer and the patterned pad oxide layer are removed to expose a surface of the substrate as an active area of the semiconductor device. An ion drive-in to the active area on the substrate is performed by directing a flow of oxygen and nitrogen toward the substrate at a predetermined temperature and with a sufficient amount of oxygen to at least substantially prevent silicon nitride from forming on the field oxide regions.
    Type: Application
    Filed: August 13, 2002
    Publication date: February 19, 2004
    Applicant: MOSEL VITELIC, INC. A Taiwanese Corporation
    Inventors: Chieh-Ju Chang, Tsai-Sen Lin, Chon-Shin Jou, Yifu Chung
  • Publication number: 20020197858
    Abstract: The present invention provides a method for fabricating semiconductor devices, which includes the following steps. First, a silicide layer is formed on a substrate. Then, the silicide layer is defined, and an oxide layer is formed uniformly on the substrate and the silicide layer. Next, the oxide layer is etched to form a sidewall oxide layer by dry etching process, and the remaining oxide layer on the substrate is removed by wet etching. Next, inactive gas is added to the surface of the silicide layer to perform an anneal process. Finally, a mask oxide layer is formed on the silicide layer.
    Type: Application
    Filed: November 21, 2001
    Publication date: December 26, 2002
    Inventors: Chieh-Ju Chang, Tsai-Sen Lin, Chon-Shin Jou, Lung-Yu Yen