Patents by Inventor Chieh-Ju TSAI

Chieh-Ju TSAI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250119995
    Abstract: The present invention discloses a boost converter power stage circuit, comprising: an organic light-emitting diode power management integrated circuit unit, a switched capacitor converter, and a boost converter, wherein, a flying capacitor is used to boost the voltage of the inductor to twice the voltage, and then the positive voltage of the output voltage source is boosted, and then use the switched capacitor converter to output the voltage in order to obtain the conversion of the negative voltage.
    Type: Application
    Filed: January 8, 2024
    Publication date: April 10, 2025
    Inventors: Ching-Jan Chen, Chieh-Ju Tsai, Sheng-Han Yu
  • Publication number: 20240313632
    Abstract: A power converter includes a power stage, a feedback circuit, a ramp generator and a controller. The power stage generates a pulse width modulation signal for forming an output voltage. The controller includes a comparator, a control logic circuit, an on-time generator and an off-time generator. The comparator generates a comparison signal according to a compensation signal from the feedback circuit and a ramp signal from the ramp generator. The control logic circuit generates a first trigger signal according to the comparison signal and an off-time pulse signal. The on-time generator generates a duty signal according to the first trigger signal. The duty signal is transmitted to the power stage for controlling a duty cycle ratio of the pulse width modulation signal. The off-time generator generates the off-time pulse signal according to the duty signal and transmits the off-time pulse signal to the control logic circuit.
    Type: Application
    Filed: August 10, 2023
    Publication date: September 19, 2024
    Inventors: Ching-Jan CHEN, Chieh-Ju TSAI, Ching-Yang WU
  • Patent number: 12088198
    Abstract: A power stage circuit generates an output signal according to an input signal and a control signal. A ramp generator circuit generates a ramp signal according to the control signal, the input signal, and the output signal. A calculation circuit generates a calculation signal according to the output signal and a reference signal. The calculation circuit operates in a first mode when the power converter operates in a light loading state, and the calculation circuit operates in a second mode when the power converter operates in a normal state. A control circuit generates the control signal according to the calculation signal and the ramp signal. The control circuit includes a comparator circuit and a control signal generator. The comparator circuit generates a comparison signal according to the calculation signal and the ramp signal. The control signal generator generates the control signal according to the comparison signal.
    Type: Grant
    Filed: December 30, 2021
    Date of Patent: September 10, 2024
    Assignee: NOVATEK Microelectronics Corp.
    Inventors: Chieh-Ju Tsai, Ching-Jan Chen, Zhen-Guo Ding, Zhe-Hui Lin, Wei-Ling Chen
  • Patent number: 11973425
    Abstract: A power converter includes a power stage circuit, a ramp generator circuit, and a control circuit. The power stage circuit generates an output signal according to an input signal and a control signal. The ramp generator circuit generates a ramp signal according to the control signal, the input signal, and the output signal. The control circuit generates the control signal according to the output signal, a reference signal, and the ramp signal.
    Type: Grant
    Filed: December 29, 2021
    Date of Patent: April 30, 2024
    Assignee: NOVATEK Microelectronics Corp.
    Inventors: Chieh-Ju Tsai, Ching-Jan Chen, Zhen-Guo Ding, Zhe-Hui Lin, Wei-Ling Chen
  • Publication number: 20220271662
    Abstract: A power stage circuit generates an output signal according to an input signal and a control signal. A ramp generator circuit generates a ramp signal according to the control signal, the input signal, and the output signal. A calculation circuit generates a calculation signal according to the output signal and a reference signal. The calculation circuit operates in a first mode when the power converter operates in a light loading state, and the calculation circuit operates in a second mode when the power converter operates in a normal state. A control circuit generates the control signal according to the calculation signal and the ramp signal. The control circuit includes a comparator circuit and a control signal generator. The comparator circuit generates a comparison signal according to the calculation signal and the ramp signal. The control signal generator generates the control signal according to the comparison signal.
    Type: Application
    Filed: December 30, 2021
    Publication date: August 25, 2022
    Inventors: Chieh-Ju TSAI, Ching-Jan CHEN, Zhen-Guo DING, Zhe-Hui LIN, Wei-Ling CHEN
  • Publication number: 20220271661
    Abstract: A power converter includes a power stage circuit, a ramp generator circuit, and a control circuit. The power stage circuit is configured to generate an output signal according to an input signal and a control signal. The ramp generator circuit is configured to generate a ramp signal according to the control signal, the input signal, and the output signal. The control circuit is configured to generate the control signal according to the output signal, a reference signal, and the ramp signal.
    Type: Application
    Filed: December 29, 2021
    Publication date: August 25, 2022
    Inventors: Chieh-Ju TSAI, Ching-Jan CHEN, Zhen-Guo DING, Zhe-Hui LIN, Wei-Ling CHEN
  • Patent number: 10879215
    Abstract: A method for manufacturing a semiconductor device package includes: (1) providing a first encapsulation layer; (2) disposing an adhesive layer on the first encapsulation layer; (3) disposing a first die on the adhesive layer; and (4) forming a second encapsulation layer covering the first die, the adhesive layer, and the first encapsulation layer.
    Type: Grant
    Filed: March 8, 2019
    Date of Patent: December 29, 2020
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Li-Hao Lyu, Chieh-Ju Tsai, Yu-Kai Lin, Wei-Ming Hsieh, Yu-Pin Tsai, Man-Wen Tseng, Yu-Ting Lu
  • Publication number: 20190206843
    Abstract: A method for manufacturing a semiconductor device package includes: (1) providing a first encapsulation layer; (2) disposing an adhesive layer on the first encapsulation layer; (3) disposing a first die on the adhesive layer; and (4) forming a second encapsulation layer covering the first die, the adhesive layer, and the first encapsulation layer.
    Type: Application
    Filed: March 8, 2019
    Publication date: July 4, 2019
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Li-Hao LYU, Chieh-Ju TSAI, Yu-Kai LIN, Wei-Ming HSIEH, Yu-Pin TSAI, Man-Wen TSENG, Yu-Ting LU
  • Patent number: 10269771
    Abstract: A semiconductor device package comprises an adhesive layer, a die on the adhesive layer, a first encapsulation layer encapsulating the die and the adhesive layer, and a second encapsulation layer adjacent to the first encapsulation layer and the adhesive layer. The second encapsulation layer has a first surface and a second surface different from the first surface. A contact angle of the first surface of the second encapsulation layer is different from a contact angle of the second surface of the second encapsulation layer.
    Type: Grant
    Filed: August 11, 2017
    Date of Patent: April 23, 2019
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Li-Hao Lyu, Chieh-Ju Tsai, Yu-Kai Lin, Wei-Ming Hsieh, Yu-Pin Tsai, Man-Wen Tseng, Yu-Ting Lu
  • Publication number: 20180061727
    Abstract: A semiconductor device package comprises an adhesive layer, a die on the adhesive layer, a first encapsulation layer encapsulating the die and the adhesive layer, and a second encapsulation layer adjacent to the first encapsulation layer and the adhesive layer. The second encapsulation layer has a first surface and a second surface different from the first surface. A contact angle of the first surface of the second encapsulation layer is different from a contact angle of the second surface of the second encapsulation layer.
    Type: Application
    Filed: August 11, 2017
    Publication date: March 1, 2018
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Li-Hao LYU, Chieh-Ju TSAI, Yu-Kai LIN, Wei-Ming HSIEH, Yu-Pin TSAI, Man-Wen TSENG, Yu-Ting LU