Patents by Inventor Chieh-Kai Yang

Chieh-Kai Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240421227
    Abstract: A method and apparatus for use in improving linearity sensitivity of MOSFET devices having an accumulated charge sink (ACS) are disclosed. The method and apparatus are adapted to address degradation in second- and third-order intermodulation harmonic distortion at a desired range of operating voltage in devices employing an accumulated charge sink.
    Type: Application
    Filed: August 26, 2024
    Publication date: December 19, 2024
    Inventors: Christopher N. Brindle, Jie Deng, Alper Genc, Chieh-Kai Yang
  • Patent number: 12074217
    Abstract: A method and apparatus for use in improving linearity sensitivity of MOSFET devices having an accumulated charge sink (ACS) are disclosed. The method and apparatus are adapted to address degradation in second- and third-order intermodulation harmonic distortion at a desired range of operating voltage in devices employing an accumulated charge sink.
    Type: Grant
    Filed: March 19, 2021
    Date of Patent: August 27, 2024
    Assignee: pSemi Corporation
    Inventors: Christopher N. Brindle, Jie Deng, Alper Genc, Chieh-Kai Yang
  • Patent number: 12022618
    Abstract: A substrate of an electronic device includes a first set of contact pads and a first set of contact pillars having a height greater than the first set of contact pads. Components are coupled to the first set of contact pads and the first set of contact pillars in traversing directions. The components coupled to the contact pillars are positioned above the components coupled to the first set of contact pads such that at least a first portion of a first side of the component coupled to the contact traces faces a first side of the components coupled to the contact pillars. Stacking passive components in this manner can allow for increased component density without increasing package size.
    Type: Grant
    Filed: April 22, 2021
    Date of Patent: June 25, 2024
    Assignee: Western Digital Technologies, Inc.
    Inventors: Chien Te Chen, Cong Zhang, Yu Ying Tan, Hsiao Jung Lin, Chieh Kai Yang
  • Patent number: 11557555
    Abstract: A bumped solder pad and methods for adding bumps to a solder pad are provided. A substrate is provided having metal layer formed thereon and a solder pad formed from a portion of the metal layer. A surface treatment is applied to the solder pad. The surface treatment is patterned. The surface treatment is etched to produce at least one bump on the solder pad.
    Type: Grant
    Filed: June 10, 2020
    Date of Patent: January 17, 2023
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Hsiao Jung Lin, Ai Wen Wang, Chien Te Chen, Chieh kai Yang
  • Publication number: 20220346234
    Abstract: A substrate of an electronic device includes a first set of contact pads and a first set of contact pillars having a height greater than the first set of contact pads. Components are coupled to the first set of contact pads and the first set of contact pillars in traversing directions. The components coupled to the contact pillars are positioned above the components coupled to the first set of contact pads such that at least a first portion of a first side of the component coupled to the contact traces faces a first side of the components coupled to the contact pillars. Stacking passive components in this manner can allow for increased component density without increasing package size.
    Type: Application
    Filed: April 22, 2021
    Publication date: October 27, 2022
    Inventors: Chien Te Chen, Cong Zhang, Yu Ying Tan, Hsiao Jung Lin, Chieh Kai Yang
  • Publication number: 20210391286
    Abstract: A bumped solder pad and methods for adding bumps to a solder pad are provided. A substrate is provided having metal layer formed thereon and a solder pad formed from a portion of the metal layer. A surface treatment is applied to the solder pad. The surface treatment is patterned. The surface treatment is etched to produce at least one bump on the solder pad.
    Type: Application
    Filed: June 10, 2020
    Publication date: December 16, 2021
    Applicant: Western Digital Technologies, Inc.
    Inventors: Hsiao Jung LIN, Ai Wen WANG, Chien Te CHEN, Chieh kai YANG
  • Publication number: 20210320206
    Abstract: A method and apparatus for use in improving linearity sensitivity of MOSFET devices having an accumulated charge sink (ACS) are disclosed. The method and apparatus are adapted to address degradation in second- and third-order intermodulation harmonic distortion at a desired range of operating voltage in devices employing an accumulated charge sink.
    Type: Application
    Filed: March 19, 2021
    Publication date: October 14, 2021
    Inventors: Christopher N. Brindle, Jie Deng, Alper Genc, Chieh-Kai Yang
  • Patent number: 11011633
    Abstract: A method and apparatus for use in improving linearity sensitivity of MOSFET devices having an accumulated charge sink (ACS) are disclosed. The method and apparatus are adapted to address degradation in second- and third-order intermodulation harmonic distortion at a desired range of operating voltage in devices employing an accumulated charge sink.
    Type: Grant
    Filed: January 9, 2020
    Date of Patent: May 18, 2021
    Assignee: pSemi Corporation
    Inventors: Christopher N. Brindle, Jie Deng, Alper Genc, Chieh-Kai Yang
  • Publication number: 20200321467
    Abstract: A method and apparatus for use in improving linearity sensitivity of MOSFET devices having an accumulated charge sink (ACS) are disclosed. The method and apparatus are adapted to address degradation in second- and third-order intermodulation harmonic distortion at a desired range of operating voltage in devices employing an accumulated charge sink.
    Type: Application
    Filed: January 9, 2020
    Publication date: October 8, 2020
    Inventors: Christopher N. Brindle, Jie Deng, Alper Genc, Chieh-Kai Yang
  • Patent number: 10797172
    Abstract: A method and apparatus for use in improving linearity sensitivity of MOSFET devices having an accumulated charge sink (ACS) are disclosed. The method and apparatus are adapted to address degradation in second- and third-order intermodulation harmonic distortion at a desired range of operating voltage in devices employing an accumulated charge sink.
    Type: Grant
    Filed: July 26, 2018
    Date of Patent: October 6, 2020
    Assignee: pSemi Corporation
    Inventors: Christopher N. Brindle, Jie Deng, Alper Genc, Chieh-Kai Yang, Michael A. Stuber, Dylan J. Kelly, Clint L. Kemerling, George Imthurn, Mark L. Burgener, Robert B. Welstand
  • Patent number: 10790390
    Abstract: A method and apparatus for use in improving linearity sensitivity of MOSFET devices having an accumulated charge sink (ACS) are disclosed. The method and apparatus are adapted to address degradation in second- and third-order intermodulation harmonic distortion at a desired range of operating voltage in devices employing an accumulated charge sink.
    Type: Grant
    Filed: April 5, 2019
    Date of Patent: September 29, 2020
    Assignee: pSemi Corporation
    Inventors: Christopher N. Brindle, Jie Deng, Alper Genc, Chieh-Kai Yang
  • Patent number: 10680590
    Abstract: A fast response time, self-activating, adjustable threshold limiter including a limiting element LE, a first coupling element CE1 electrically connected from a signal node of LE to a control input of LE, and a second coupling element CE2 electrically connected from the control input of LE to a nominal node of LE. An initial bias (control) voltage is also supplied to the control input of LE to dynamically control the limiting threshold for the limiter. Embodiments include usage of self-activating adjustable power limiters in combination with series switch components in a switch circuit in lieu of conventional shunt switches.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: June 9, 2020
    Assignee: pSemi Corporation
    Inventors: Jianhua Lu, Naveen Yanduru, Edward Nicholas Comfoltey, Michael Conry, Chieh-Kai Yang
  • Patent number: 10629733
    Abstract: A method and apparatus for use in improving linearity sensitivity of MOSFET devices having an accumulated charge sink (ACS) are disclosed. The method and apparatus are adapted to address degradation in second- and third-order intermodulation harmonic distortion at a desired range of operating voltage in devices employing an accumulated charge sink.
    Type: Grant
    Filed: July 26, 2018
    Date of Patent: April 21, 2020
    Assignee: pSemi Corporation
    Inventors: Christopher N. Brindle, Jie Deng, Alper Genc, Chieh-Kai Yang
  • Publication number: 20190296722
    Abstract: A fast response time, self-activating, adjustable threshold limiter including a limiting element LE, a first coupling element CE1 electrically connected from a signal node of LE to a control input of LE, and a second coupling element CE2 electrically connected from the control input of LE to a nominal node of LE. An initial bias (control) voltage is also supplied to the control input of LE to dynamically control the limiting threshold for the limiter. Embodiments include usage of self-activating adjustable power limiters in combination with series switch components in a switch circuit in lieu of conventional shunt switches.
    Type: Application
    Filed: March 29, 2019
    Publication date: September 26, 2019
    Inventors: Jianhua Lu, Naveen Yanduru, Edward Nicholas Comfoltey, Michael Conry, Chieh-Kai Yang
  • Publication number: 20190237579
    Abstract: A method and apparatus for use in improving linearity sensitivity of MOSFET devices having an accumulated charge sink (ACS) are disclosed. The method and apparatus are adapted to address degradation in second- and third-order intermodulation harmonic distortion at a desired range of operating voltage in devices employing an accumulated charge sink.
    Type: Application
    Filed: April 5, 2019
    Publication date: August 1, 2019
    Inventors: Christopher N. Brindle, Jie Deng, Alper Genc, Chieh-Kai Yang
  • Patent number: 10277211
    Abstract: A fast response time, self-activating, adjustable threshold limiter including a limiting element LE, a first coupling element CE1 electrically connected from a signal node of LE to a control input of LE, and a second coupling element CE2 electrically connected from the control input of LE to a nominal node of LE. An initial bias (control) voltage is also supplied to the control input of LE to dynamically control the limiting threshold for the limiter. Embodiments include usage of self-activating adjustable power limiters in combination with series switch components in a switch circuit in lieu of conventional shunt switches.
    Type: Grant
    Filed: November 30, 2016
    Date of Patent: April 30, 2019
    Assignee: pSemi Corporation
    Inventors: Jianhua Lu, Peter Bacon, Naveen Yanduru, Edward Nicholas Comfoltey, Michael Conry, Chieh-Kai Yang
  • Publication number: 20190088781
    Abstract: A method and apparatus for use in improving linearity sensitivity of MOSFET devices having an accumulated charge sink (ACS) are disclosed. The method and apparatus are adapted to address degradation in second- and third-order intermodulation harmonic distortion at a desired range of operating voltage in devices employing an accumulated charge sink.
    Type: Application
    Filed: July 26, 2018
    Publication date: March 21, 2019
    Inventors: Christopher N. Brindle, Jie Deng, Alper Genc, Chieh-Kai Yang
  • Patent number: 10224913
    Abstract: A fast response time, self-activating, adjustable threshold limiter including a limiting element LE, a first coupling element CE1 electrically connected from a signal node of LE to a control input of LE, and a second coupling element CE2 electrically connected from the control input of LE to a nominal node of LE. An initial bias (control) voltage is also supplied to the control input of LE to dynamically control the limiting threshold for the limiter. Embodiments include usage of self-activating adjustable power limiters in combination with series switch components in a switch circuit in lieu of conventional shunt switches.
    Type: Grant
    Filed: November 30, 2016
    Date of Patent: March 5, 2019
    Assignee: pSemi Corporation
    Inventors: Jianhua Lu, Peter Bacon, Naveen Yanduru, Edward Nicholas Comfoltey, Michael Conry, Chieh-Kai Yang
  • Patent number: 10074746
    Abstract: A method and apparatus for use in improving linearity sensitivity of MOSFET devices having an accumulated charge sink (ACS) are disclosed. The method and apparatus are adapted to address degradation in second- and third-order intermodulation harmonic distortion at a desired range of operating voltage in devices employing an accumulated charge sink.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: September 11, 2018
    Assignee: pSemi Corporation
    Inventors: Christopher N. Brindle, Jie Deng, Alper Genc, Chieh-Kai Yang
  • Publication number: 20180061985
    Abstract: A method and apparatus for use in improving linearity sensitivity of MOSFET devices having an accumulated charge sink (ACS) are disclosed. The method and apparatus are adapted to address degradation in second- and third-order intermodulation harmonic distortion at a desired range of operating voltage in devices employing an accumulated charge sink.
    Type: Application
    Filed: August 31, 2017
    Publication date: March 1, 2018
    Inventors: Christopher N. Brindle, Jie Deng, Alper Genc, Chieh-Kai Yang