Abstract: A method for timestamping and synchronization with high-accuracy timestamps in low-power sensor systems is provided. The method is performed by a device and includes: receiving, by a sensor hub of the device, an interrupt signal from a sensor and performing an interrupt service routine (ISR) to obtain an interrupt timestamp obtained by a latch, wherein the interrupt timestamp is obtained from an always-running unified time reference; obtaining, by the sensor hub, sensor data from the sensor; predicting, by the sensor hub, a prediction timestamp based on an amount of sensor data and the interrupt timestamp by using a filtering algorithm; and correcting, by the sensor hub, a timestamp of each sensor data based on the prediction timestamp.

Abstract: A method for timestamping and synchronization with high-accuracy timestamps in low-power sensor systems is provided. The method is performed by a device and includes: receiving, by a sensor hub of the device, an interrupt signal from a sensor and performing an interrupt service routine (ISR) to obtain an interrupt timestamp obtained by a latch, wherein the interrupt timestamp is obtained from an always-running unified time reference; obtaining, by the sensor hub, sensor data from the sensor; predicting, by the sensor hub, a prediction timestamp based on an amount of sensor data and the interrupt timestamp by using a filtering algorithm; and correcting, by the sensor hub, a timestamp of each sensor data based on the prediction timestamp.

Abstract: A training system and a training method of reinforcement learning are disclosed. The training system includes a first computer device and a second computer device, and the computing power of the second computer device is better than that of the first computer device. The first computer device stores a reinforcement learning model; receives input data; and feeds the input data into the reinforcement learning model to generate a first output result. The second computer device stores a supervised learning model; receives the input data from the first computer device; feeds the input data into the supervised learning model to generate a second output result; and transmits the second output result to the first computer device. The first computer device further generates reward data according to the first output result and the second output result, and trains the reinforcement learning model according to the reward data.

Abstract: A memory management system includes a memory, a processor, a memory access monitoring module and a memory management module. The processor is used to access the memory. The memory access monitoring module includes a first terminal coupled to the processor, and a second terminal coupled to the memory. The memory access monitoring module is used to monitor whether the processor has accessed the memory so as to generate monitor data. The memory management module is used to receive the monitor data and predict when the memory is to be accessed according to at least the monitor data.

Abstract: A memory management system includes a memory, a processor, a memory access monitoring module and a memory management module. The processor is used to access the memory. The memory access monitoring module includes a first terminal coupled to the processor, and a second terminal coupled to the memory. The memory access monitoring module is used to monitor whether the processor has accessed the memory so as to generate monitor data. The memory management module is used to receive the monitor data and predict when the memory is to be accessed according to at least the monitor data.

Abstract: A microcontroller includes a processor, a memory, a working space management unit and a memory monitor. The memory has at least a working space, wherein the working space includes a plurality of blocks . The working space management unit is implemented by software, and is arranged for managing the working space of the first memory. The memory monitor is implemented by hardware circuit, and is arranged for monitoring the blocks, and recording monitoring results corresponding to the blocks of the first memory, wherein the recorded monitoring results comprise information about whether data of the blocks is modified or not.

Abstract: A microcontroller includes a processor, a memory, a working space management unit and a memory monitor. The memory has at least a working space, wherein the working space includes a plurality of blocks. The working space management unit is implemented by software, and is arranged for managing the working space of the first memory. The memory monitor is implemented by hardware circuit, and is arranged for monitoring the blocks, and recording monitoring results corresponding to the blocks of the first memory, wherein the recorded monitoring results comprise information about whether data of the blocks is modified or not.

Abstract: A multiplication circuit generates a product of a matrix and a first scalar when in matrix mode and a product of a second scalar and a third scalar when in scalar mode. The multiplication circuit comprises a sub-product generator, an accumulator and an adder. The adder is configured to sum outputs of the accumulator to generate the product of the first scalar second scalar and the third scalar when in scalar mode. The sub-product generator generates sub-products of the matrix and the first scalar when in matrix mode and sub-products of the second scalar and the third scalar when in scalar mode. The accumulator is configured to generate the product of the matrix and the first scalar by providing save of the multiplication operation of the outputs from the sub-product generator.

Abstract: A heterogeneous memory architecture includes a first memory, a second memory and a memory controller. The first memory has a first memory space. The second memory has a second memory space larger than the first memory space. The memory controller is used for accessing common address space of the first memory and the second memory in a 2X-bit bandwidth, and for disabling the first memory and accessing non-common address space of the second memory in opposite to the first memory in a X-bit bandwidth, X being a positive integer.

Abstract: A multiplication circuit generates a product of a matrix and a first scalar when in matrix mode and a product of a second scalar and a third scalar when in scalar mode. The multiplication circuit comprises a sub-product generator, an accumulator and an adder. The adder is configured to sum outputs of the accumulator to generate the product of the first scalar second scalar and the third scalar when in scalar mode. The sub-product generator generates sub-products of the matrix and the first scalar when in matrix mode and sub-products of the second scalar and the third scalar when in scalar mode. The accumulator is configured to generate the product of the matrix and the first scalar by providing save of the multiplication operation of the outputs from the sub-product generator.