Abstract: An interface control circuit complying with an interface specification includes: an interface signal transceiver circuit and a protection circuit. The interface signal transceiver circuit is coupled to a first interface connection pin and a second interface connection pin of a first interface connector circuit. The interface signal transceiver circuit is for transmitting and/or receiving an interface signal according to the interface specification. When the interface signal transceiver circuit operates under a first state, the protection circuit determines whether a foreign object exists between the first interface connection pin and the second interface connection pin according to a voltage change or a current change at the second interface connection pin. Under the first state, the interface signal transceiver circuit generates a pull-up signal and a pull-down signal which are toggled with each other at the first interface connection pin.

Abstract: An interface control circuit complying with an interface specification includes: an interface signal transceiver circuit and a protection circuit. The interface signal transceiver circuit is coupled to a first interface connection pin and a second interface connection pin of a first interface connector circuit. The interface signal transceiver circuit is for transmitting and/or receiving an interface signal according to the interface specification. When the interface signal transceiver circuit operates under a first state, the protection circuit determines whether a foreign object exists between the first interface connection pin and the second interface connection pin according to a voltage change or a current change at the second interface connection pin. Under the first state, the interface signal transceiver circuit generates a pull-up signal and a pull-down signal which are toggled with each other at the first interface connection pin.

Abstract: A power supply system includes a power supplier circuit and a power receiver circuit. The power supplier circuit supplies a power via a communication interface compatible with a first communication interface specification or a second communication interface specification. The first communication interface specification includes a delay threshold. After the power supplier circuit is coupled to the power receiver circuit, the power supplier circuit supplies the power after a first delay period. The power receiver circuit confirms whether the power supplier circuit is coupled to the power receiver circuit via a coupling confirmation step according to the first communication interface specification. The power receiver circuit confirms whether the power supplier circuit is compatible with the first communication interface specification or the second communication interface specification according to whether the first delay period is greater than the delay threshold.

Abstract: An interface control circuit comprises an interface signal transceiver circuit coupled with an interface which includes at least one interface pin for transmitting and/or receiving an interface signal through the interface, and a protection circuit for generating a protection control signal according to a capacitance of a first interface pin. During a predetermined detection time period starting from an attaching event, the protection circuit senses the capacitance of the first interface pin, and determines that there is an electrolytic substance existing and coupled with the first interface pin when the capacitance is larger than a predetermined first capacitance threshold. The protection control signal triggers the interface signal transceiver circuit to execute a protection operation. The interface includes the first interface pin and the second interface pin, and the first interface pin and the second interface pin can be one same pin or separate different pins.

Abstract: A power supply system includes a power supplier circuit and a power receiver circuit. The power supplier circuit supplies a power via a communication interface compatible with a first communication interface specification or a second communication interface specification. The first communication interface specification includes a delay threshold. After the power supplier circuit is coupled to the power receiver circuit, the power supplier circuit supplies the power after a first delay period. The power receiver circuit confirms whether the power supplier circuit is coupled to the power receiver circuit via a coupling confirmation step according to the first communication interface specification. The power receiver circuit confirms whether the power supplier circuit is compatible with the first communication interface specification or the second communication interface specification according to whether the first delay period is greater than the delay threshold.

Abstract: An interface control circuit includes an interface signal transceiver circuit and a protection circuit. The interface signal transceiver circuit transmits and/or receives an interface signal through a transmission interface which includes at least a first interface pin. The protection circuit includes a switch and a comparison circuit. The switch controls a conduction between the first interface pin and a signal source. The comparison circuit senses a voltage of the first interface pin, and determines whether the voltage of the first interface pin is within a threshold voltage range which corresponds to a foreign object attachment event, whereby the interface signal transceiver circuit is triggered to execute a protection operation.

Abstract: An operation mode determination circuit for sensing a setting resistance between a setting node and a reference voltage or a ground to determine an operation mode, comprises: a pull-up power circuit, for generating a pull-up power onto the setting node, and a floating detection circuit. The pull-up power circuit adjusts the pull-up power at a first power level, and triggers an low power detach detection procedure after a predetermined first time period, wherein the pull-up power is adjusted at a second power level which is less than the first power level to an extent that an electrolysis effect is negligible when an electrolytic substance exists and is coupled to the setting node. The floating detection circuit triggers the operation mode detection procedure when the voltage on the setting node is higher than a first voltage threshold in the low power detach detection procedure.

Abstract: An operation mode determination circuit for sensing a setting resistance between a setting node and a reference voltage or a ground to determine an operation mode, comprises: a pull-up power circuit, for generating a pull-up power onto the setting node, and a floating detection circuit. The pull-up power circuit adjusts the pull-up power at a first power level, and triggers an low power detach detection procedure after a predetermined first time period, wherein the pull-up power is adjusted at a second power level which is less than the first power level to an extent that an electrolysis effect is negligible when an electrolytic substance exists and is coupled to the setting node. The floating detection circuit triggers the operation mode detection procedure when the voltage on the setting node is higher than a first voltage threshold in the low power detach detection procedure.

Abstract: An interface control circuit comprises an interface signal transceiver circuit coupled with an interface which includes at least one interface pin for transmitting and/or receiving an interface signal through the interface, and a protection circuit for generating a protection control signal according to a capacitance of a first interface pin. During a predetermined detection time period starting from an attaching event, the protection circuit senses the capacitance of the first interface pin, and determines that there is an electrolytic substance existing and coupled with the first interface pin when the capacitance is larger than a predetermined first capacitance threshold. The protection control signal triggers the interface signal transceiver circuit to execute a protection operation. The interface includes the first interface pin and the second interface pin, and the first interface pin and the second interface pin can be one same pin or separate different pins.

Abstract: The present invention discloses a rail-to-rail comparator. The rail-to-rail comparator includes: a positive voltage rail providing a positive supply voltage, a ground voltage rail providing a ground voltage, an input stage, and an output stage. The input stage includes: a positive and a negative input terminals for receiving a first input signal and a second input signal; a first differential amplifier circuit, which includes a pair of depletion NMOS transistors to generate a first pair of differential currents; and a second differential amplifier circuit, which includes a pair of native NMOS transistors to generate a second pair of differential currents. The output stage is coupled to the first differential amplifier circuit and the second differential amplifier circuit, and generates an output signal related to a difference between the first input signal and the second input signal.

Abstract: The present invention discloses a rail-to-rail comparator. The rail-to-rail comparator includes: a positive voltage rail providing a positive supply voltage, a ground voltage rail providing a ground voltage, an input stage, and an output stage. The input stage includes: a positive and a negative input terminals for receiving a first input signal and a second input signal; a first differential amplifier circuit, which includes a pair of depletion NMOS transistors to generate a first pair of differential currents; and a second differential amplifier circuit, which includes a pair of native NMOS transistors to generate a second pair of differential currents. The output stage is coupled to the first differential amplifier circuit and the second differential amplifier circuit, and generates an output signal related to a difference between the first input signal and the second input signal.

Abstract: The present invention discloses a linear regulator and a control circuit therefor. The linear regulator includes: a power device coupled between an input voltage and an output voltage; a first error amplifier including a depletion NMOS differential circuit comparing a feedback signal related to the output voltage with a reference signal; a second error amplifier including a native NMOS differential circuit comparing the feedback signal with the reference signal; and a start-up circuit which enables the first error amplifier to dominate control and drive the power device when the linear regulator is at a first stage of a start-up period and enables the second error amplifier to dominate control and drive the power device when the linear regulator is at a second stage after the first stage.