Patents by Inventor Chieh-Ning Feng

Chieh-Ning Feng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240387430
    Abstract: Semiconductor structures and methods are provided. An exemplary semiconductor structure includes a contact pad over a substrate, an under-bump metallization (UBM) layer over the contact pad, a metal pillar over first UBM layer and electrically coupled to the contact pad via the UBM layer, and a solder cap on the metal pillar. The metal pillar comprises copper, and a percentage of (111) crystal orientation of the copper is 90% or more.
    Type: Application
    Filed: August 4, 2023
    Publication date: November 21, 2024
    Inventors: Chang-Jung Hsueh, Chieh-Ning Feng, Yu-Lun Liu, Wen-Hsiung Lu, Ming-Da Cheng
  • Publication number: 20240387539
    Abstract: A method for making a semiconductor device includes forming a first fin structure including a first plurality of semiconductor layers vertically spaced from one another and over a substrate; forming a second fin structure including a second plurality of semiconductor layers vertically spaced from one another and over the substrate, the first and the second fin structures extend along a first lateral direction; forming a first dielectric structure extending into the substrate and parallel with the first and second fin structures, the second fin structure being separated from the first fin structure along a second lateral direction perpendicular to the first lateral direction, by a first distance; and forming a first gate structure that extends along the second lateral direction and wraps around each of the first plurality of semiconductor layers and each of the second plurality of semiconductor layers.
    Type: Application
    Filed: July 29, 2024
    Publication date: November 21, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Yao Lin, Chen-Ping Chen, Chieh-Ning Feng, Hsiao Wen Lee, Chih-Han Lin
  • Publication number: 20240371702
    Abstract: A method includes forming a dielectric fin over a substrate between a first semiconductor fin and a second semiconductor fin. The first and second semiconductor fins, and the dielectric fin all extend along a first lateral direction. The method includes forming a dummy gate structure that extends along a second lateral direction and includes a first portion and a second portion. The first and second portions overlay the first and second semiconductor fins, respectively, and separate from each other with the dielectric fin. The method includes removing upper sidewall portions of the dielectric fin. The method includes replacing the first and second portions of the dummy gate structure with a first and second active gate structures, respectively.
    Type: Application
    Filed: July 12, 2024
    Publication date: November 7, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Yao Lin, Chieh-Ning Feng, Hsiao Wen Lee, Ming-Ching Chang
  • Publication number: 20240363431
    Abstract: A method of forming a semiconductor device includes forming a first fin and a second fin protruding above a substrate; forming isolation regions on opposing sides of the first fin and the second fin; forming a metal gate over the first fin and over the second fin, the metal gate being surrounded by a first dielectric layer; and forming a recess in the metal gate between the first fin and the second fin, where the recess extends from an upper surface of the metal gate distal the substrate into the metal gate, where the recess has an upper portion distal the substrate and a lower portion between the upper portion and the substrate, where the upper portion has a first width, and the lower portion has a second width larger than the first width, the first width and the second width measured along a longitudinal direction of the metal gate.
    Type: Application
    Filed: July 9, 2024
    Publication date: October 31, 2024
    Inventors: Chih-Chang Hung, Chieh-Ning Feng, Chun-Liang Lai, Yih-Ann Lin, Ryan Chia-Jen Chen
  • Publication number: 20240347534
    Abstract: A method for making a semiconductor device includes: forming a first semiconductor fin structure and a second semiconductor fin structure over a substrate that both extend along a first lateral direction; forming a dummy gate structure that extends along a second lateral direction perpendicular to the first direction and straddles the first and second semiconductor fin structures; removing a portion of the dummy gate structure between the first and second semiconductor fin structures to form a trench, a width of the trench along the second direction decreasing with increasing depth toward the substrate; filling the trench with a dielectric material; and removing the second semiconductor fin structure and a portion of the dielectric material.
    Type: Application
    Filed: June 20, 2024
    Publication date: October 17, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company Ltd.
    Inventors: Shu-Uei Jang, Shih-Yao Lin, Chieh-Ning Feng, Shu-Yuan Ku
  • Publication number: 20240321880
    Abstract: A semiconductor device includes a dielectric fin between a first semiconductor channel and a second semiconductor channel. The semiconductor device includes a first gate structure. The first gate structure includes a first portion and a second portion separated from each other by the dielectric fin. The semiconductor device includes a first gate spacer that extends along sidewalls of the first portion of the first gate structure. The semiconductor device includes a second gate spacer that extends along sidewalls of the second portion of the first gate structure, respectively. At least one of the first gate spacer or second gate spacer has a first portion with a first thickness and a second portion with a second thickness less than the first thickness, and wherein the first portion is closer to the dielectric fin than the second portion.
    Type: Application
    Filed: June 3, 2024
    Publication date: September 26, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Yao Lin, Chieh-Ning Feng, Hsiao Wen Lee, Chao-Cheng Chen
  • Patent number: 12094782
    Abstract: A method includes forming a dielectric fin over a substrate between a first semiconductor fin and a second semiconductor fin. The first and second semiconductor fins, and the dielectric fin all extend along a first lateral direction. The method includes forming a dummy gate structure that extends along a second lateral direction and includes a first portion and a second portion. The first and second portions overlay the first and second semiconductor fins, respectively, and separate from each other with the dielectric fin. The method includes removing upper sidewall portions of the dielectric fin. The method includes replacing the first and second portions of the dummy gate structure with a first and second active gate structures, respectively.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: September 17, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shih-Yao Lin, Chieh-Ning Feng, Hsiao Wen Lee, Ming-Ching Chang
  • Patent number: 12087639
    Abstract: A method of forming a semiconductor device includes forming a first fin and a second fin protruding above a substrate; forming isolation regions on opposing sides of the first fin and the second fin; forming a metal gate over the first fin and over the second fin, the metal gate being surrounded by a first dielectric layer; and forming a recess in the metal gate between the first fin and the second fin, where the recess extends from an upper surface of the metal gate distal the substrate into the metal gate, where the recess has an upper portion distal the substrate and a lower portion between the upper portion and the substrate, where the upper portion has a first width, and the lower portion has a second width larger than the first width, the first width and the second width measured along a longitudinal direction of the metal gate.
    Type: Grant
    Filed: August 9, 2022
    Date of Patent: September 10, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Chang Hung, Chieh-Ning Feng, Chun-Liang Lai, Yih-Ann Lin, Ryan Chia-Jen Chen
  • Patent number: 12046597
    Abstract: A semiconductor device includes a substrate; a semiconductor fin structure disposed over the substrate, wherein the semiconductor fin structure extend along a first lateral direction; a gate structure that straddles a semiconductor fin structure, wherein the gate structure extends along a second lateral direction, the first lateral direction perpendicular to the second lateral direction; a dielectric fin structure that extends along the first lateral direction and is disposed next to the semiconductor structure fin structure; and a gate isolation structure disposed above the dielectric fin structure. The gate isolation structure contacts an upper portion of the gate structure at a first tilted interface.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: July 23, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shu-Uei Jang, Shih-Yao Lin, Chieh-Ning Feng, Shu-Yuan Ku
  • Patent number: 12027521
    Abstract: A semiconductor device includes a dielectric fin between a first semiconductor channel and a second semiconductor channel. The semiconductor device includes a first gate structure. The first gate structure includes a first portion and a second portion separated from each other by the dielectric fin. The semiconductor device includes a first gate spacer that extends along sidewalls of the first portion of the first gate structure. The semiconductor device includes a second gate spacer that extends along sidewalls of the second portion of the first gate structure. At least one of the first gate spacer or second gate spacer has a first portion with a first thickness and a second portion with a second thickness less than the first thickness, and wherein the first portion is closer to the dielectric fin than the second portion.
    Type: Grant
    Filed: March 12, 2021
    Date of Patent: July 2, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Yao Lin, Chieh-Ning Feng, Hsiao Wen Lee, Chao-Cheng Chen
  • Publication number: 20240213029
    Abstract: Methods for forming a CPODE structure with reduced leakage current are disclosed herein. The CPODE structure is formed by etching away a pair of fins and forming a pair of trenches in the substrate where the pair of fins was originally located. A leakage path may be present in the area between the pair of fins. The etching is performed by cycling continuously plasma etch until the trenches are formed. The plasma etch removes any byproducts that may be formed during the fin etch which could reduce or stop the etching of the fins, the area between the pair of fins, and the substrate.
    Type: Application
    Filed: January 4, 2023
    Publication date: June 27, 2024
    Inventors: Tzu-Ging Lin, Yi-Chun Chen, Chieh-Ning Feng, Jih-Jse Lin
  • Publication number: 20240120207
    Abstract: A semiconductor package includes a die having a plurality of devices over a first substrate, where the first substrate includes a dopant at a first concentration and the first substrate has a first width along a horizontal direction. The semiconductor package further includes a second substrate fused with the first substrate, where the second substrate includes the dopant at a second concentration greater than the first concentration.
    Type: Application
    Filed: February 15, 2023
    Publication date: April 11, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Lung-Kai Mao, Wen-Hsiung Lu, Pei-Wei Lee, Szu-Hsien Lee, Chieh-Ning Feng
  • Publication number: 20230343783
    Abstract: A semiconductor device includes a first semiconductor fin and a second semiconductor fin extending along a first direction. The semiconductor device includes a dielectric fin, extending along the first direction, that is disposed between the first and second semiconductor fins. The semiconductor device includes a gate isolation structure vertically disposed above the dielectric fin. The semiconductor device includes a metal gate layer extending along a second direction perpendicular to the first direction, wherein the metal gate layer includes a first portion straddling the first semiconductor fin and a second portion straddling the second semiconductor fin. The gate isolation structure has a central portion and one or more side portions, the central portion extends toward the dielectric fin a further distance than at least one of the one or more side portions.
    Type: Application
    Filed: June 30, 2023
    Publication date: October 26, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ya-Yi Tsai, Wen-Shuo Hsieh, Shu-Yuan Ku, Chieh-Ning Feng
  • Patent number: 11715736
    Abstract: A semiconductor device includes a first semiconductor fin and a second semiconductor fin extending along a first direction. The semiconductor device includes a dielectric fin, extending along the first direction, that is disposed between the first and second semiconductor fins. The semiconductor device includes a gate isolation structure vertically disposed above the dielectric fin. The semiconductor device includes a metal gate layer extending along a second direction perpendicular to the first direction, wherein the metal gate layer includes a first portion straddling the first semiconductor fin and a second portion straddling the second semiconductor fin. The gate isolation structure has a central portion and one or more side portions, the central portion extends toward the dielectric fin a further distance than at least one of the one or more side portions.
    Type: Grant
    Filed: June 23, 2021
    Date of Patent: August 1, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ya-Yi Tsai, Wen-Shuo Hsieh, Shu-Yuan Ku, Chieh-Ning Feng
  • Publication number: 20230063087
    Abstract: A method includes forming a first, second, third, fourth, fifth, and sixth fin structure. The second fin structure is separated from each of the first and third fin structures by a first distance, the fifth fin structure is separated from each of the fourth and sixth fin structures by the first distance, and the third fin structure is separated from the fourth fin structure by a second distance greater than the first distance. The method includes forming a first dummy gate structure overlaying the first through third fin structures, and a second dummy gate structure overlaying the fourth through sixth fin structures; forming a number of source/drain structures that are coupled to the first, second, third, fourth, fifth, and sixth fin structures, respectively; and replacing the third fin structure with a first dielectric structure, and replacing the fourth fin structure with a second dielectric structure.
    Type: Application
    Filed: August 27, 2021
    Publication date: March 2, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Yao Lin, Chen-Ping Chen, Chieh-Ning Feng, Hsiao Wen Lee, Chih-Han Lin
  • Publication number: 20230067859
    Abstract: A semiconductor device includes a plurality of first channel layers vertically spaced from one another and a plurality of second channel layers vertically spaced form one another. Each of the plurality of first and second channel layers extend along a first lateral direction. The semiconductor device includes an isolation structure disposed between the plurality of first channel layers and the plurality of second channel layers along a second lateral direction perpendicular to the first lateral direction. The semiconductor device includes a plurality of inner spacers discretely disposed along a first sidewall of the isolation structure that faces toward the first lateral direction, or discretely disposed along a second sidewall of the isolation structure that faces away from the first lateral direction wherein an interface between each of the plurality of inner spacers and the first or second sidewall has a vertical profile.
    Type: Application
    Filed: February 15, 2022
    Publication date: March 2, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Yao Lin, Chieh-Ning Feng, Hsiaowen Lee, Ming-Ching Chang
  • Publication number: 20230061497
    Abstract: A method includes forming a dielectric fin over a substrate between a first semiconductor fin and a second semiconductor fin. The first and second semiconductor fins, and the dielectric fin all extend along a first lateral direction. The method includes forming a dummy gate structure that extends along a second lateral direction and includes a first portion and a second portion. The first and second portions overlay the first and second semiconductor fins, respectively, and separate from each other with the dielectric fin. The method includes removing upper sidewall portions of the dielectric fin. The method includes replacing the first and second portions of the dummy gate structure with a first and second active gate structures, respectively.
    Type: Application
    Filed: August 30, 2021
    Publication date: March 2, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Yao LIN, Chieh-Ning Feng, Hsiao Wen Lee, Ming-Ching Chang
  • Publication number: 20230066828
    Abstract: A semiconductor device includes a substrate; a semiconductor fin structure disposed over the substrate, wherein the semiconductor fin structure extend along a first lateral direction; a gate structure that straddles a semiconductor fin structure, wherein the gate structure extends along a second lateral direction, the first lateral direction perpendicular to the second lateral direction; a dielectric fin structure that extends along the first lateral direction and is disposed next to the semiconductor structure fin structure; and a gate isolation structure disposed above the dielectric fin structure. The gate isolation structure contacts an upper portion of the gate structure at a first tilted interface.
    Type: Application
    Filed: August 30, 2021
    Publication date: March 2, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shu-Uei Jang, Shih-Yao Lin, Chieh-Ning Feng, Shu-Yuan Ku
  • Publication number: 20220415886
    Abstract: A semiconductor device includes a first semiconductor fin and a second semiconductor fin extending along a first direction. The semiconductor device includes a dielectric fin, extending along the first direction, that is disposed between the first and second semiconductor fins. The semiconductor device includes a gate isolation structure vertically disposed above the dielectric fin. The semiconductor device includes a metal gate layer extending along a second direction perpendicular to the first direction, wherein the metal gate layer includes a first portion straddling the first semiconductor fin and a second portion straddling the second semiconductor fin. The gate isolation structure has a central portion and one or more side portions, the central portion extends toward the dielectric fin a further distance than at least one of the one or more side portions.
    Type: Application
    Filed: June 23, 2021
    Publication date: December 29, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company Ltd.
    Inventors: YA-YI TSAI, Wen-Shuo Hsieh, Shu-Yuan Ku, Chieh-Ning Feng
  • Publication number: 20220384271
    Abstract: A method of forming a semiconductor device includes forming a first fin and a second fin protruding above a substrate; forming isolation regions on opposing sides of the first fin and the second fin; forming a metal gate over the first fin and over the second fin, the metal gate being surrounded by a first dielectric layer; and forming a recess in the metal gate between the first fin and the second fin, where the recess extends from an upper surface of the metal gate distal the substrate into the metal gate, where the recess has an upper portion distal the substrate and a lower portion between the upper portion and the substrate, where the upper portion has a first width, and the lower portion has a second width larger than the first width, the first width and the second width measured along a longitudinal direction of the metal gate.
    Type: Application
    Filed: August 9, 2022
    Publication date: December 1, 2022
    Inventors: Chih-Chang Hung, Chieh-Ning Feng, Chun-Liang Lai, Yih-Ann Lin, Ryan Chia-Jen Chen