Patents by Inventor Chieh-Pu Lo
Chieh-Pu Lo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230333582Abstract: A power regulation system including a reference generator, a temperature compensation circuit coupled to the reference generator, and a low-dropout (LDO) regulator circuit coupled to the temperature compensation circuit, wherein the temperature compensation circuit provides a reference voltage to the LDO regulator circuit at least based on a ratio of a first current and a second current.Type: ApplicationFiled: June 21, 2023Publication date: October 19, 2023Applicant: Taiwan Semiconductor Manufacturing Company LimitedInventors: Yen-An CHANG, Chieh-Pu LO, Yi-Chun SHIH, Chia-Fu LEE, Yu-Der CHIH
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Patent number: 11720130Abstract: A power regulation system including a reference generator, a temperature compensation circuit coupled to the reference generator, and a low-dropout (LDO) regulator circuit coupled to the temperature compensation circuit, wherein the temperature compensation circuit provides a reference voltage to the LDO regulator circuit at least based on a ratio of a first current and a second current.Type: GrantFiled: August 9, 2021Date of Patent: August 8, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITEDInventors: Yen-An Chang, Chieh-Pu Lo, Yi-Chun Shih, Chia-Fu Lee, Yu-Der Chih
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Publication number: 20220269483Abstract: A compute-in memory (CIM) device is configured to determine at least one input according to a type of an application and at least one weight according to a training result or a configuration of a user. The CIM device performs a bit-serial multiplication based on the input and the weight, from a most significant bit (MSB) of the input to a least significant bit (LSB) of the input to obtain a result according to a plurality of partial-products. A first partial-sum of a first bit of the input is left shifted one bit and then added with a second partial-product of a second bit of the input to obtain a second partial-sum of the second bit. The second bit is one bit after the first bit, and the result is output by the CIM device.Type: ApplicationFiled: December 21, 2021Publication date: August 25, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chieh-Pu Lo, Po-Hao Lee, Yi-Chun Shih
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Publication number: 20220179439Abstract: A reference voltage generator includes an input terminal configured to receive an enable signal and an output terminal configured to provide an output signal. A voltage generator circuit is arranged to generate a first output voltage signal, and a pre-settling circuit is arranged to generate a second output voltage. The pre-settling circuit is configured to provide the second output voltage signal at the output terminal in response to the enable signal received at the input terminal, and following a first time period provide the first output voltage at the output terminal.Type: ApplicationFiled: February 28, 2022Publication date: June 9, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yen-An Chang, Yi-Chun Shih, Chieh-Pu Lo
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Patent number: 11262778Abstract: A reference voltage generator includes an input terminal configured to receive an enable signal and an output terminal configured to provide an output signal. A voltage generator circuit is arranged to generate a first output voltage signal, and a pre-settling circuit is arranged to generate a second output voltage. The pre-settling circuit is configured to provide the second output voltage signal at the output terminal in response to the enable signal received at the input terminal, and following a first time period provide the first output voltage at the output terminal.Type: GrantFiled: April 24, 2020Date of Patent: March 1, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yen-An Chang, Yi-Chun Shih, Chieh-Pu Lo
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Publication number: 20210365060Abstract: A power regulation system including a reference generator, a temperature compensation circuit coupled to the reference generator, and a low-dropout (LDO) regulator circuit coupled to the temperature compensation circuit, wherein the temperature compensation circuit provides a reference voltage to the LDO regulator circuit at least based on a ratio of a first current and a second current.Type: ApplicationFiled: August 9, 2021Publication date: November 25, 2021Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yen-An CHANG, Chieh-Pu LO, Yi-Chun SHIH, Chia-Fu LEE, Yu-Der CHIH
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Patent number: 11137785Abstract: In an embodiment, a voltage regulation circuit includes a regulation circuit with a voltage regulator that provides an output voltage and a control circuit, coupled to the voltage regulator. The control circuit pulls up the output voltage to a reference voltage responsive to the control circuit detecting that a first voltage level of the output voltage is lower than a predefined voltage level. The control circuit decouples the output voltage from the reference voltage responsive to the control circuit detecting that the first voltage level of the output voltage is higher than the predefined voltage level.Type: GrantFiled: February 11, 2020Date of Patent: October 5, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITEDInventors: Yen-An Chang, Chieh-Pu Lo, Yi-Chun Shih, Chia-Fu Lee, Yu-Der Chih
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Publication number: 20210247789Abstract: In an embodiment, a voltage regulation circuit includes a regulation circuit with a voltage regulator that provides an output voltage and a control circuit, coupled to the voltage regulator. The control circuit pulls up the output voltage to a reference voltage responsive to the control circuit detecting that a first voltage level of the output voltage is lower than a predefined voltage level. The control circuit decouples the output voltage from the reference voltage responsive to the control circuit detecting that the first voltage level of the output voltage is higher than the predefined voltage level.Type: ApplicationFiled: February 11, 2020Publication date: August 12, 2021Inventors: Yen-An Chang, Chieh-Pu Lo, Yi-Chun Shih, Chia-Fu Lee, Yu-Der Chih
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Publication number: 20200409402Abstract: A reference voltage generator includes an input terminal configured to receive an enable signal and an output terminal configured to provide an output signal. A voltage generator circuit is arranged to generate a first output voltage signal, and a pre-settling circuit is arranged to generate a second output voltage. The pre-settling circuit is configured to provide the second output voltage signal at the output terminal in response to the enable signal received at the input terminal, and following a first time period provide the first output voltage at the output terminal.Type: ApplicationFiled: April 24, 2020Publication date: December 31, 2020Inventors: Yen-An Chang, Yi-Chun Shih, Chieh-Pu Lo
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Patent number: 9722584Abstract: Provided is a non-volatile latch, which includes a latch circuit, a first switch circuit, a non-volatile memory device, a second switch circuit and a third switch circuit. A first terminal of the first switch circuit is coupled to a first output terminal of the latch circuit. The first switch circuit is turned off in a normal operation period. A first terminal of the non-volatile memory device is coupled to a second terminal of the first switch circuit. A second terminal of the non-volatile memory device is coupled to a programming voltage via the second switch circuit. In a store period, according to latched data of the latch circuit and a state transformation condition of the non-volatile memory device, the third switch circuit can dynamically determine whether to couple the first terminal of the non-volatile memory device to a reference voltage.Type: GrantFiled: April 20, 2016Date of Patent: August 1, 2017Assignee: National Tsing Hua UniversityInventors: Meng-Fan Chang, Albert Lee, Chieh-Pu Lo, Chien-Chen Lin
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Patent number: 9564209Abstract: A non-volatile SRAM cell comprises a first inverter, a second inverter, a first access transistor, a second access transistor, and a variable resistive element. The first inverter voltage is supplied by a first differential supply. The second inverter voltage is supplied by a second differential supply. The variable resistive element coupling with a third access transistor in series is coupled to the first output node. The non-volatile SRAM cell operates in a restore operation comprising a dual supply initialization phase and a pulse-overwrite phase. During the dual supply initialization phase, the first differential supply increases before the second differential supply so as to initialize the first output node to a logic state. During the pulse-overwrite phase, the third access transistor is turned on for a switch period in order to discharge/charge the first output node.Type: GrantFiled: September 22, 2015Date of Patent: February 7, 2017Assignee: NATIONAL TSING HUA UNIVERSITYInventors: Albert Lee, Chien-Chen Lin, Chieh-Pu Lo, Meng-Fan Chang
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Patent number: 9502114Abstract: A cell for a non-volatile ternary content-addressable (TCAM) memory is provided. The cell comprises a first variable resistive element, a first transistor and a charge control transistor. Two terminals of the first variable resistive element are respectively electrically coupled to a first search-line and a storage node. A drain electrode of the first transistor is electrically coupled to the storage node. A source electrode of the first transistor is electrically coupled to a low-side search-line. A gate electrode of the charge control transistor coupled to a match-line is electrically coupled to the storage node. When the cell operates in a search phase and the first transistor is turned on, a pulse voltage is applied across the first search-line and the low-side search-line for determining whether the voltage of the storage node is larger than a match threshold during the period of the pulse.Type: GrantFiled: November 14, 2015Date of Patent: November 22, 2016Assignee: NATIONAL TSING HUA UNIVERSITYInventors: Chien-Chen Lin, Albert Lee, Chieh-Pu Lo, Meng-Fan Chang