Patents by Inventor Chieh-Ting Chen
Chieh-Ting Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250188639Abstract: A method of manufacturing a structure having anodized parts includes: forming a bottom metal layer on a substrate; forming a top metal layer on the bottom metal layer; forming a mask layer on the top metal layer to expose a portion of a top surface of the top metal layer; etching the top metal layer through the mask layer until a top surface of the bottom metal layer is exposed, wherein an etch selectivity of the top metal layer and the bottom metal layer is greater than 2.0; anodizing the bottom metal layer through the mask layer to form an anodized segment; and removing the mask layer after the anodizing.Type: ApplicationFiled: December 6, 2023Publication date: June 12, 2025Inventors: Li-Yi CHEN, Chieh-Ting CHEN
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Publication number: 20250188638Abstract: A method of manufacturing a structure having anodized parts includes: forming a bottom metal pattern with a dielectric layer thereon on a substrate, in which the dielectric layer has an opening exposing the bottom metal pattern; forming a semiconductor layer to cover the dielectric layer; forming a first metal layer on the semiconductor layer; forming a second metal layer on the first metal layer; forming a mask layer on the second metal layer to expose a portion of a top surface of the second metal layer; etching the second metal layer through the mask layer until a top surface of the first metal layer is exposed, in which an etch selectivity of the second metal layer and the first metal layer is greater than 2.0; anodizing the first metal layer through the mask layer to form an anodized segment; and removing the mask layer.Type: ApplicationFiled: December 6, 2023Publication date: June 12, 2025Inventors: Li-Yi CHEN, Chieh-Ting CHEN
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Publication number: 20250191922Abstract: A method of forming an electrode with multi-dielectric layers includes: forming a metal pattern on a substrate, in which the metal pattern includes a first metal film on the substrate and a second metal film on a top surface of the first metal film, and the first and second metal films have different metal compositions; and anodizing the metal pattern in a liquid electrolyte to form a covering anodized portion which covers an unanodized portion, in which the covering anodized portion includes a sidewall oxide dielectric structure and a top oxide dielectric structure, the sidewall oxide dielectric structure is in contact with a side surface of the unanodized portion, the top oxide dielectric structure is in contact with top surfaces of the unanodized portion and the sidewall oxide dielectric structure, and the sidewall and top oxide dielectric structures have different effective permittivities.Type: ApplicationFiled: December 6, 2023Publication date: June 12, 2025Inventors: Li-Yi CHEN, Chieh-Ting CHEN
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Publication number: 20250194304Abstract: A method of manufacturing an electrode structure includes: etching the bottom metal layer through a first patterned photoresist including first and second mask portions to form a first metal pattern, a second metal pattern, and a bridge connected therebetween; removing the first mask portion; anodizing the bottom metal layer with the remained second mask portion by flowing an anodizing current from the first metal pattern; removing the remained second mask portion; depositing a conductive layer on the bottom metal layer to be in contact with an area of the second metal pattern that is unanodized; etching the conductive layer through a second patterned photoresist until an open segment of the bridge is exposed; and etching the open segment of the bridge through the second patterned photoresist until the bridge is electrically opened.Type: ApplicationFiled: December 6, 2023Publication date: June 12, 2025Inventors: Li-Yi CHEN, Chieh-Ting CHEN
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Publication number: 20250191923Abstract: A method of manufacturing a structure having an electrode and an anodized part includes: forming a top metal layer on a substrate; forming a top patterned photoresist on the top metal layer to expose a portion of a top surface of the top metal layer, in which the top patterned photoresist has a first mask portion and a second mask portion thicker than the first mask portion; anodizing the top metal layer through the top patterned photoresist to form an anodized segment; removing the first mask portion after the anodizing; and etching the top metal layer through the top patterned photoresist after the removing the first mask portion to form a top metal pattern.Type: ApplicationFiled: December 6, 2023Publication date: June 12, 2025Inventors: Li-Yi CHEN, Chieh-Ting CHEN
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Publication number: 20250191924Abstract: A method of manufacturing a structure having an electrode and an anodized part includes: forming a top metal layer on a substrate; forming a top patterned photoresist on the top metal layer to expose a portion of a top surface of the top metal layer, in which the top patterned photoresist has a first mask portion and a second mask portion thicker than the first mask portion; anodizing the top metal layer through the top patterned photoresist to form an anodized segment; removing the first mask portion after the anodizing; etching the top metal layer through the top patterned photoresist after the removing the first mask portion to form a top metal pattern; and reflowing the top patterned photoresist after the anodizing and before the etching.Type: ApplicationFiled: December 6, 2023Publication date: June 12, 2025Inventors: Li-Yi CHEN, Chieh-Ting CHEN
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Publication number: 20250191931Abstract: A method of manufacturing a structure having multi metal layers includes: depositing a top metal layer on a bottom metal layer; forming a patterned photoresist on the top metal layer; etching the top and bottom metal layers through first hollow portions of the patterned photoresist to respectively form a top metal pattern and a bottom metal pattern; forming a second hollow portion in the patterned photoresist to expose a portion of the top metal pattern; etching the top metal pattern through the second hollow portion until a top surface portion of the bottom metal pattern is exposed by the etched top metal pattern, in which an etch selectivity of the top and bottom metal layers in the etching the top metal pattern is greater than 1.0; and anodizing the top surface portion to form an anodized segment of the bottom metal layer.Type: ApplicationFiled: December 6, 2023Publication date: June 12, 2025Inventors: Li-Yi CHEN, Chieh-Ting CHEN
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Publication number: 20250191932Abstract: A method of manufacturing an interconnection structure includes: forming a first patterned photoresist on a bottom metal layer; etching the bottom metal layer to form first and second lower metal patterns; partially anodizing the etched bottom metal layer; removing the first patterned photoresist to expose a surface portion of the second lower metal pattern that is unanodized; depositing a conductive layer on the anodized bottom metal layer to be in contact with the surface portion; and etching the conductive layer through a second patterned photoresist to form a first upper conductive pattern that is above and electrically isolated from the first lower metal pattern and a second upper conductive pattern that is above the second lower metal pattern and in contact with the surface portion, in which the first and second upper conductive patterns entirely cover all non-insulated top surface of the anodized bottom metal layer.Type: ApplicationFiled: December 6, 2023Publication date: June 12, 2025Inventors: Li-Yi CHEN, Chieh-Ting CHEN
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Patent number: 8110931Abstract: A wafer defines a plurality of chips arranged in array manner. Each chip includes at least one aluminum pad and a middle material. The middle material covers the aluminum pad and is mounted on the aluminum pad.Type: GrantFiled: July 10, 2009Date of Patent: February 7, 2012Assignee: Advanced Semiconductor Engineering, Inc.Inventors: Hsiao Chuan Chang, Tsung Yueh Tsai, Yi Shao Lai, Ho Ming Tong, Jian Cheng Chen, Wei Chi Yih, Chang Ying Hung, Cheng Wei Huang, Chih Hsing Chen, Tai Yuan Huang, Chieh Ting Chen, Yi Tsai Lu
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Patent number: 7834969Abstract: A multi-domain vertical alignment (MVA) liquid crystal display panel includes an array substrate, a color filter (CF) substrate arranged in parallel to the array substrate, a plurality of bump patterns disposed on the CF substrate, and a plurality of transparent electrode patterns disposed on the array substrate. Each bump pattern includes a main bump corresponding to a pixel region, and at least one bump wing corresponding to a scan line or a data line. Each main bump includes a first protrusion connected to a side of the main bump. Each transparent electrode pattern includes a main slit. The transparent electrode pattern further includes a plurality of fine slits disposed in an inner side and in an outer side of the main slit. The fine slits disposed in the outer side of the main slit near the data line have different lengths.Type: GrantFiled: November 17, 2006Date of Patent: November 16, 2010Assignee: AU Optronics Corp.Inventors: Chia-Jung Yang, Jenn-Jia Su, Chieh-Ting Chen, Ting-Jui Chang
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Publication number: 20100007004Abstract: A wafer defines a plurality of chips arranged in array manner. Each chip includes at least one aluminum pad and a middle material. The middle material covers the aluminum pad and is mounted on the aluminum pad.Type: ApplicationFiled: July 10, 2009Publication date: January 14, 2010Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Hsiao Chuan CHANG, Tsung Yueh Tsai, Yi Shao Lai, Ho Ming Tong, Jian cheng Chen, Wei Chi Yih, Chang Ying Hung, Cheng Wei Huang, Chih Hsing Chen, Tai Yuan Huang, Chieh Ting Chen, Yi Tsai Lu
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Patent number: 7400368Abstract: Liquid crystal displays and fabrication methods thereof. The liquid crystal display comprises a first substrate with an active matrix of a plurality of pixels. A second substrate is provided opposing the first substrate. A liquid crystal layer is interposed between the first substrate and the second substrate. Each pixel comprises a polymer dispersed liquid crystal layer corresponding to a first liquid crystal region and a non-polymer dispersed liquid crystal layer corresponding to a second liquid crystal region.Type: GrantFiled: October 4, 2005Date of Patent: July 15, 2008Assignee: Au Optronics Corp.Inventors: Yi-Ju Chen, Chia-Yu Lee, Chieh-Ting Chen, Po-Lun Chen
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Patent number: 7327929Abstract: A backlight module including a first light guide plate, a first light source, a second light guide plate, and a second light source. The first light guide plate includes a first side, a second side opposite to the first side, and a first surface with a micro-groove structure. The first light source is disposed on the first side of the first light guide plate. The second light guide plate is disposed on the first light guide plate, and includes a third side, a fourth side opposite to the third side, and a second surface with a micro-groove structure. The fourth side and the second side are located at the same side. The second light source is disposed on the fourth side of the second light guide plate.Type: GrantFiled: June 7, 2005Date of Patent: February 5, 2008Assignee: Au Optronics Corp.Inventors: Ko-Wei Chien, Yu-Mioun Chu, Han-Ping Shieh, Chih-Jen Hu, Ching-Sang Yang, Yi-Cheng Hsu, Chieh-Ting Chen, Chih-Ming Chang, Yung-Lun Lin, Meng-Chang Tsai, Ching-Huan Lin, Mu-Jen Su, Hsiu-Chi Tung
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Publication number: 20080024706Abstract: A multi-domain vertical alignment (MVA) liquid crystal display panel includes an array substrate, a color filter (CF) substrate arranged in parallel to the array substrate, a plurality of bump patterns disposed on the CF substrate, and a plurality of transparent electrode patterns disposed on the array substrate. Each bump pattern includes a main bump corresponding to a pixel region, and at least one bump wing corresponding to a scan line or a data line. Each main bump includes a first protrusion connected to a side of the main bump. Each transparent electrode pattern includes a main slit. The transparent electrode pattern further includes a plurality of fine slits disposed in an inner side and in an outer side of the main slit. The fine slits disposed in the outer side of the main slit near the data line have different lengths.Type: ApplicationFiled: November 17, 2006Publication date: January 31, 2008Inventors: Chia-Jung Yang, Jenn-Jia Su, Chieh-Ting Chen, Ting-Jui Chang
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Publication number: 20060203147Abstract: Liquid crystal displays and fabrication methods thereof. The liquid crystal display comprises a first substrate with an active matrix of a plurality of pixels. A second substrate is provided opposing the first substrate. A liquid crystal layer is interposed between the first substrate and the second substrate. Each pixel comprises a polymer dispersed liquid crystal layer corresponding to a first liquid crystal region and a non-polymer dispersed liquid crystal layer corresponding to a second liquid crystal region.Type: ApplicationFiled: October 4, 2005Publication date: September 14, 2006Inventors: Yi-Ju Chen, Chia-Yu Lee, Chieh-Ting Chen, Po-Lun Chen
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Publication number: 20060164862Abstract: A backlight module including a first light guide plate, a first light source, a second light guide plate, and a second light source. The first light guide plate includes a first side, a second side opposite to the first side, and a first surface with a micro-groove structure. The first light source is disposed on the first side of the first light guide plate. The second light guide plate is disposed on the first light guide plate, and includes a third side, a fourth side opposite to the third side, and a second surface with a micro-groove structure. The fourth side and the second side are located at the same side. The second light source is disposed on the fourth side of the second light guide plate.Type: ApplicationFiled: June 7, 2005Publication date: July 27, 2006Inventors: Ko-Wei Chien, Yu-Mioun Chu, Han-Ping Shieh, Chih-Jen Hu, Ching-Sang Yang, Yi-Cheng Hsu, Chieh-Ting Chen, Chih-Ming Chang, Yung-Lun Lin, Meng-Chang Tsai, Ching-Huan Lin, Mu-Jen Su, Hsiu-Chi Tung