Abstract: An electronic device includes a logic body, a heat dissipation fin, and a rotating bracket. The logic body has multiple first end openings and multiple first bottom openings. The first end openings are disposed on a first end of the logic body. The first bottom openings are disposed on a bottom of the logic body and are adjacent to the first end. The heat dissipation fins are disposed inside an interior of the logic body and correspond to the first bottom openings. The rotating bracket is rotatably disposed at the bottom. In a closed mode, the rotating bracket is close to the bottom and covers the first bottom openings. In an open mode, the rotating bracket is unfolded from the bottom and exposes the first bottom openings.

Abstract: One aspect of the present disclosure pertains to a semiconductor device. The semiconductor device includes a semiconductor substrate and a transistor formed over the semiconductor substrate. The transistor includes a first source/drain (S/D) feature, a second S/D feature, a channel region interposed between the first and second S/D features, and a gate stack engaging the channel region. The semiconductor device includes a first S/D contact landing on a top surface of the first S/D feature, a second S/D contact landing on a top surface of the second S/D feature, and a dielectric plug penetrating through the semiconductor substrate and landing on a bottom surface of the first S/D feature. The dielectric plug spans a width equal to or smaller than a width of the first S/D feature.

Abstract: A thermal dissipation holder for a handheld electronic device is provided. The thermal dissipation holder includes a main structure, a movable element, an elastic element, and a locker. The main structure has a front surface and a rear surface. The movable element is movably connected to the main structure along a first direction and has a clamp portion at a side away from the carrier. One end of the elastic element is connected to the main structure. The other end of the elastic element is connected to the movable element. The elastic element drives the movable element to move along the first direction. The locker is disposed in the main structure and has a locking portion, where a position of the locking portion corresponds to that of the clamp portion, and the locker is selectively engaged with the clamp portion through the locking portion to lock the movable element.

Abstract: The present invention provides a key plugging structure, a key assembly and a keyboard. The key plugging structure includes a circuit board, a socket member and an elastic member. The circuit board includes a through hole penetrating through the circuit board. The socket member includes a slot and a first jack hole, the first jack hole is formed at the bottom of the slot; the socket member is embedded in the through hole; the first jack hole and the through hole are connected to each other; the elastic member has a second jack hole; the elastic member is assembled in the hole slot; the second socket hole and the first socket hole are connected with each other. Further, the key assembly includes a key. The redesign for the socket of the key plugging structure embedded in the circuit board reduce the height of the key assembly.

Abstract: A virtual and real integrated medical teaching assistance system based on mixed reality and a method thereof are disclosed.

Abstract: A semiconductor die and the method of forming the same are provided. The semiconductor die includes a first interconnect structure, a second interconnect structure including a conductive feature, and a device layer between the first interconnect structure and the second interconnect structure. The device layer includes a semiconductor fin, a first gate structure on the semiconductor fin, a source/drain region adjacent the first gate structure, and a shared contact extending through the semiconductor fin to be electrically connected to the source/drain region and the first gate structure. The conductive feature contacts the shared contact.

Abstract: Methods for chemical mechanical polishing (CMP), and methods for forming an interconnect structure of a semiconductor device are provided. The methods include performing CMP on a surface of a dielectric structure with a CMP slurry to remove a portion of a metal layer formed in the dielectric structure and having at least a first layer exposed through the surface. In some examples, the CMP slurry that includes an abrasive, an oxidizing agent, and a compound configured to reduce aggregation of the abrasive on the surface of the dielectric structure. In some examples, the compound has positively charged ions that interact with the abrasive to reduce aggregation of the abrasive on a dielectric material. In some examples, the CMP slurry includes potassium hydroxide. In some examples, the compound includes an ammonium salt.

Abstract: An exemplary device includes a frontside power rail disposed over a frontside of a substrate, a backside power rail disposed over a backside of the substrate, an epitaxial source/drain structure disposed between the frontside power rail and the backside power rail. The epitaxial source/drain structure is connected to the frontside power rail by a frontside source/drain contact. The epitaxial source/drain structure is connected to the backside power rail by a backside source/drain via. The backside source/drain via is disposed in a substrate, and a dielectric layer is disposed between the substrate and the backside power rail. The backside source/drain via extends through the dielectric layer and the substrate.

Abstract: A locking pliers includes a first plier and a second plier. The first plier includes a first handle, a first jaw, and an adjusting member. The second plier includes a second jaw, a first connecting member, a toggle link, and a second handle. The second jaw has a first pivoting portion and a second pivoting portion. The first pivoting portion is pivotally connected to the first handle. The first connecting member is pivotally connected to the second pivoting portion. The toggle link is abutted against the adjusting member and has a third pivoting portion pivotally connected to the first connecting member. The second handle is connected to the first connecting member. A first length defined between the first pivoting portion and the second pivoting portion is less than a second length defined between the second pivoting portion and the third pivoting portion.

Abstract: A gamma tap circuit includes: (i) a first gamma division circuit configured to generate a first gamma tap voltage by performing voltage division of an upper gamma tap voltage and a lower gamma tap voltage, in-sync with a first clock signal CK1 and a first complementary clock signal CK1b, which is 180° out-of-phase relative to CK1, (ii) a second gamma division circuit configured to generate a second gamma tap voltage by performing voltage division of the upper gamma tap voltage and the first gamma tap voltage, in-sync with a second clock signal CK2 and a second complementary clock signal CK2b, which is 180° out-of-phase relative to CK2, and (iii) a third gamma division circuit configured to generate a third gamma tap voltage by performing voltage division of the first gamma tap voltage and the lower gamma tap voltage, in response to CK2 and CK2b, which have a lower frequency relative to CK1 and CK1b.

Abstract: Implementations of the present disclosure provide coloring methods that sort and pre-color nodes of G0-linked networks in a multiple-patterning technology (MPT)-compliant layout design by coordinate. In one embodiment, a method includes identifying target networks in a circuit layout, each target network having two or more linked nodes representing circuit patterns, and each target network being presented in an imaginary X-Y coordinate plane, assigning a first feature to a first node in each target network, the first node is determined using a coordinate-based method, and assigning the first feature and a second feature to remaining nodes in each target network in an alternating manner so that any two immediately adjacent linked nodes in each target network have different features.

Abstract: A semiconductor device structure includes nanostructures formed over a substrate. The structure also includes a gate structure formed over and around the nanostructures. The structure also includes a spacer layer formed over a sidewall of the gate structure over the nanostructures. The structure also includes a source/drain epitaxial structure formed adjacent to the spacer layer. The structure also includes a contact structure formed over the source/drain epitaxial structure with an air spacer formed between the spacer layer and the contact structure.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a source/drain region formed in a semiconductor substrate, a source/drain contact structure formed over the source/drain region, and a silicide region formed between the source/drain region and the source/drain contact structure. The semiconductor device structure also includes a first insulating spacer surrounding and in direct contact with the source/drain contact structure and a second insulating spacer and a third insulating spacer respectively formed on two opposite sidewalls of the source/drain contact structure and in direct contact with an outer edge of the first insulating spacer. A first sidewall of the second insulating spacer and a second sidewall of the third insulating spacer are respectively aligned to two opposite side edges of the source/drain region.

Abstract: A semiconductor structure includes a first die; a plurality of first conductive vias adjacent to the first die. The semiconductor structure further includes a plurality of second conductive vias disposed over the first conductive vias, each of the second conductive vias corresponding to one of the first conductive vias; a plurality of third conductive vias disposed over the first die; and a molding material encapsulating the first die, the first conductive vias, the second conductive vias and the third conductive vias. A first width of each of the plurality of first conductive vias, a second width of each of the plurality of second conductive vias and a third width of the plurality of third conductive vias are different from each other.

Abstract: In an embodiment, a method includes: forming a first fin extending from a substrate; forming a second fin extending from the substrate, the second fin being spaced apart from the first fin by a first distance; forming a metal gate stack over the first fin and the second fin; depositing a first inter-layer dielectric over the metal gate stack; and forming a gate contact extending through the first inter-layer dielectric to physically contact the metal gate stack, the gate contact being laterally disposed between the first fin and the second fin, the gate contact being spaced apart from the first fin by a second distance, where the second distance is less than a second predetermined threshold when the first distance is greater than or equal to a first predetermined threshold.

Abstract: One aspect of the present disclosure pertains to a method of forming a semiconductor device. The method includes forming a gate stack over a channel region and forming a first source/drain (S/D) trench adjacent the channel region and extending into the substrate below a top surface of an isolation structure. The method includes forming a first epitaxial S/D feature in the first S/D trench and forming a first frontside metal contact over the first epitaxial S/D feature. The method further includes forming a first backside trench that exposes a bottom surface of the first epitaxial S/D feature and forming a first backside conductive feature in the first backside trench and on the exposed bottom surface of the first epitaxial S/D feature. A top surface of the first backside conductive feature is under a bottommost surface of the gate stack.

Abstract: An automotive decorative panel includes a decorative film, a touch icon component, and a light source system. The decorative film has an optical density between 0.2 and 2.0 and includes a substrate and a decorative layer disposed on the substrate. The touch icon component is disposed under the decorative film and includes a light-shielding pattern layer having an optical density between 3.5 and 6.0, a light diffusion layer disposed under the light-shielding pattern layer, and a touch layer. The light-shielding pattern layer has a pattern area that is light-permeable and a peripheral area that is light-impermeable. The touch layer is disposed on a side of the light-shielding pattern layer or between the decorative film and the light-shielding pattern layer. The light source system is disposed on a side of the touch icon component and configured to emit light toward the touch icon component.

Abstract: A method includes generating a diffraction map from a plurality of target patterns, generating a favorable zone and an unfavorable zone from the diffraction map, placing a plurality of sub-resolution patterns in the favorable zone, and performing a plurality of geometric operations on the plurality of sub-resolution patterns to generate modified sub-resolution patterns. The modified sub-resolution patterns extend into the favorable zone, and are away from the unfavorable zone.

Abstract: A semiconductor structure includes a first die; a second die disposed over the first die; a plurality of first conductive vias adjacent to the first die. The semiconductor structure further includes a plurality of second conductive vias disposed over the first conductive vias, each of the second conductive vias corresponding to one of the first conductive vias; a plurality of third conductive vias disposed over the first die and adjacent to the second die; and a molding material encapsulating the first die, the second die, the first conductive vias, the second conductive vias and the third conductive vias. A stepped shape is formed around an interface between each of the first conductive vias and the corresponding one of the second conductive vias.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a source/drain region formed in a semiconductor substrate, a source/drain contact structure formed over the source/drain region, and a gate electrode layer formed adjacent to the source/drain contact structure. The semiconductor device structure also includes a first spacer and a second spacer laterally and successively arranged from the sidewall of the gate electrode layer to the sidewall of the source/drain contact structure. The semiconductor device structure further includes a silicide region formed in the source/drain region. The top width of the silicide region is greater than the bottom width of the source/drain contact structure and less than the top width of the source/drain region.