Abstract: A balloon catheter system assisted by ultrasound and microbubbles and a method for vasodilation are provided. The system includes: a controller; a sensor catheter; a highly focused ultrasound probe, and the highly focused ultrasound probe and the sensor catheter is connected to the controller; and a balloon catheter. The method of vasodilation includes: providing a sensor catheter into a blood vessel, and controlling a highly focused ultrasound probe to focus at a hardened portion of the blood vessel; removing the sensor catheter from the blood vessel and inserting a balloon catheter into the blood vessel; infusing microbubbles into the balloon catheter and controlling the highly focused ultrasound probe to start working to destroy a calcification point of the hardened portion of the blood vessel, and smoothly inflating the balloon catheter at the hardened portion of the blood vessel.

Abstract: A balloon catheter system assisted by ultrasound and microbubbles and a method for vasodilation are provided. The system includes: a controller; a sensor catheter; a highly focused ultrasound probe, and the highly focused ultrasound probe and the sensor catheter is connected to the controller; and a balloon catheter. The method of vasodilation includes: providing a sensor catheter into a blood vessel, and controlling a highly focused ultrasound probe to focus at a hardened portion of the blood vessel; removing the sensor catheter from the blood vessel and inserting a balloon catheter into the blood vessel; infusing microbubbles into the balloon catheter and controlling the highly focused ultrasound probe to start working to destroy a calcification point of the hardened portion of the blood vessel, and smoothly inflating the balloon catheter at the hardened portion of the blood vessel.

Abstract: A Mask ROM is shown, including first resistors as a first part of memory cells, second resistors as a second part of memory cells, and contact plugs. Each first resistor includes: an undoped first poly-Si layer including an upper horizontal bar, a lower horizontal bar contiguous with the upper horizontal bar, and a step structure with a step height at which the two bars are contiguous, a spacer on the sidewall of the step structure, and a first silicide layer on the first poly-Si layer and being divided apart by the spacer. Each second resistor includes an undoped second poly-Si layer, and a contiguous second silicide layer on the second poly-Si layer. The contact plugs are disposed on the first silicide layer on the upper horizontal bar of each first poly-Si layer, and on the second silicide layer.

Abstract: A Mask ROM is shown, including first resistors as a first part of memory cells, second resistors as a second part of memory cells, and contact plugs. Each first resistor includes: an undoped first poly-Si layer including a convex portion and a step structure with a step height adjacent to the convex portion, a spacer on the sidewall of the step structure, and a first silicide layer on the first poly-Si layer and being divided apart by the spacer. Each second resistor includes an undoped second poly-Si layer, and a contiguous second silicide layer on the second poly-Si layer. The contact plugs are disposed on the first silicide layer on the convex portion of each first poly-Si layer, and on the second silicide layer.

Abstract: The present invention provides a LCOS device including a silicon substrate, a first dielectric layer, a first mirror layer, a second dielectric layer, and a second mirror layer. The first dielectric layer is disposed on the silicon substrate. The first mirror layer is disposed on the first dielectric layer. The second dielectric layer is disposed on the first mirror layer. The second mirror layer is disposed on the second dielectric layer.

Abstract: The present invention provides a LCOS device including a silicon substrate, a first dielectric layer, a first mirror layer, a second dielectric layer, and a second mirror layer. The first dielectric layer is disposed on the silicon substrate. The first mirror layer is disposed on the first dielectric layer. The second dielectric layer is disposed on the first mirror layer. The second minor layer is disposed on the second dielectric layer.

Abstract: A method for forming spacers of different sizes includes the following steps. First a substrate is provided, which has a first element, a second element, a first material layer and a second material layer thereon. A first dry etching is performed to remove part of the second material layer to form a first spacer by the first element and to form a second side wall by the second element, so that the first material layer between the first spacer and the second side wall is exposed to become a damaged first material layer. A trimming procedure is performed to trim the damaged first material layer. A mask is used to cover the first element, the first spacer and part of the first material layer then a wet etching is performed to remove the second side wall.

Abstract: A method for forming spacers of different sizes includes the following steps. First a substrate is provided, which has a first element, a second element, a first material layer and a second material layer thereon. A first dry etching is performed to remove part of the second material layer to form a first spacer by the first element and to form a second side wall by the second element, so that the first material layer between the first spacer and the second side wall is exposed to become a damaged first material layer. A trimming procedure is performed to trim the damaged first material layer. A mask is used to cover the first element, the first spacer and part of the first material layer then a wet etching is performed to remove the second side wall.

Abstract: A multilayer diplexer has a first I/O terminal, a second I/O terminal, an antenna terminal, a high-pass filter coupled between the antenna terminal and the second I/O terminal, and a low-pass filter coupled between the antenna terminal and the first I/O terminal. The high-pass filter has a first capacitor and a second capacitor connected in serial coupled between the antenna terminal and the second I/O terminal, a fourth capacitor coupled between the antenna terminal and the second I/O terminal, and a first inductor coupled between a connection node of the first and second capacitors and a reference ground. The low-pass filter has a second inductor coupled between the antenna terminal and the first I/O terminal, and a third and fifth capacitor connected in parallel coupled between the antenna terminal and the first I/O terminal.