Patents by Inventor Chieh-Yuan Chi
Chieh-Yuan Chi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10403567Abstract: A method for fabricating an electronic package is provided, which includes the steps of: providing an insulating layer having at least an electronic element embedded therein; forming at least a first via hole on one side of the insulating layer; forming a first conductor in the first via hole of the insulating layer; forming on the insulating layer a first circuit structure electrically connected to the electronic element and the first conductor; and forming a second via hole on the other side of the insulating layer, wherein the second via hole communicates with the first via hole. As such, the second via hole and the first via hole constitute a through hole. Since the through hole is fabricated through two steps, the aspect ratio (depth/width) of the through hole can be adjusted according to the practical need so as to improve the process yield.Type: GrantFiled: January 9, 2018Date of Patent: September 3, 2019Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Yan-Heng Chen, Chun-Tang Lin, Mu-Hsuan Chan, Chieh-Yuan Chi
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Publication number: 20180130727Abstract: A method for fabricating an electronic package is provided, which includes the steps of: providing an insulating layer having at least an electronic element embedded therein; forming at least a first via hole on one side of the insulating layer; forming a first conductor in the first via hole of the insulating layer; forming on the insulating layer a first circuit structure electrically connected to the electronic element and the first conductor; and forming a second via hole on the other side of the insulating layer, wherein the second via hole communicates with the first via hole. As such, the second via hole and the first via hole constitute a through hole. Since the through hole is fabricated through two steps, the aspect ratio (depth/width) of the through hole can be adjusted according to the practical need so as to improve the process yield.Type: ApplicationFiled: January 9, 2018Publication date: May 10, 2018Inventors: Yan-Heng Chen, Chun-Tang Lin, Mu-Hsuan Chan, Chieh-Yuan Chi
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Patent number: 9899303Abstract: A method for fabricating an electronic package is provided, which includes the steps of: providing an insulating layer having at least an electronic element embedded therein; forming at least a first via hole on one side of the insulating layer; forming a first conductor in the first via hole of the insulating layer; forming on the insulating layer a first circuit structure electrically connected to the electronic element and the first conductor; and forming a second via hole on the other side of the insulating layer, wherein the second via hole communicates with the first via hole. As such, the second via hole and the first via hole constitute a through hole. Since the through hole is fabricated through two steps, the aspect ratio (depth/width) of the through hole can be adjusted according to the practical need so as to improve the process yield.Type: GrantFiled: September 23, 2015Date of Patent: February 20, 2018Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Yan-Heng Chen, Chun-Tang Lin, Mu-Hsuan Chan, Chieh-Yuan Chi
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Patent number: 9842758Abstract: A method for fabricating a package structure is provided, including the steps of: disposing on a carrier a semiconductor chip having an active surface facing the carrier; forming a patterned resist layer on the carrier; forming on the carrier an encapsulant exposing an inactive surface of the semiconductor chip and a surface of the patterned resist layer; and removing the carrier to obtain a package structure. Thereafter, redistribution layers can be formed on the opposite sides of the package structure, and a plurality of through holes can be formed in the patterned resist layer by drilling, thus allowing a plurality of conductive through holes to be formed in the through holes for electrically connecting the redistribution layers on the opposite sides of the package structure. Therefore, the invention overcomes the conventional drawback of surface roughness of the through holes caused by direct drilling the encapsulant having filler particles.Type: GrantFiled: August 26, 2015Date of Patent: December 12, 2017Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Yan-Heng Chen, Chun-Tang Lin, Chieh-Yuan Chi
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Patent number: 9768140Abstract: A method for fabricating a package structure is provided, which includes the steps of: providing an encapsulant encapsulating at least an electronic element; forming a shaping layer on a surface of the encapsulant, wherein the shaping layer has at least an opening exposing a portion of the surface of the encapsulant; forming at least a through hole corresponding in position to the opening and penetrating the encapsulant; and forming a conductor in the through hole. The shaping layer facilitates to prevent deformation of the through hole.Type: GrantFiled: October 16, 2014Date of Patent: September 19, 2017Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Yan-Heng Chen, Mu-Hsuan Chan, Chieh-Yuan Chi
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Patent number: 9607941Abstract: A method for fabricating a conductive via structure is provided, which includes the steps of: forming in an encapsulant a plurality of openings penetrating therethrough; forming a dielectric layer on the encapsulant and in the openings of the encapsulant; forming a plurality of vias in the dielectric layer in the openings of the encapsulant; and forming a conductive material in the vias to thereby form conductive vias. Therefore, by filling the openings having rough wall surfaces with the dielectric layer so as to form the vias having even wall surfaces, the present invention improves the quality of the conductive vias.Type: GrantFiled: March 26, 2015Date of Patent: March 28, 2017Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Yan-Heng Chen, Chun-Tang Lin, Chieh-Yuan Chi, Mu-Hsuan Chan
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Patent number: 9548219Abstract: A carrier structure is provided, which includes: a metal oxide plate having opposite first and second surfaces and a plurality of through holes penetrating the first and second surfaces; a plurality of conductive portions formed in the through holes, respectively; and a plurality of conductive pads formed on the first surface of the metal oxide plate, wherein each of the conductive pads is correspondingly positioned on and in contact with a plurality of the conductive portions so as to be electrically connected to the plurality of the conductive portions. By replacing a conventional silicon interposer with the metal oxide plate, the present invention eliminates the need to form through silicon vias as required in the prior art and therefore simplifies the fabrication process.Type: GrantFiled: December 29, 2014Date of Patent: January 17, 2017Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Yan-Heng Chen, Chung-Tang Lin, Chieh-Yuan Chi
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Patent number: 9515040Abstract: A method for fabricating a package structure is provided, including the steps of: sequentially forming a metal layer and a dielectric layer on a first carrier, wherein the dielectric layer has a plurality of openings exposing portions of the metal layer; disposing an electronic element on the dielectric layer via an active surface thereof and mounting a plurality of conductive elements of metal balls on the exposed portions of the metal layer; forming an encapsulant on the dielectric layer for encapsulating the electronic element and the conductive elements; removing the first carrier; and patterning the metal layer into first circuits and forming second circuits on the dielectric layer, wherein the second circuits are electrically connected to the electronic element and the first circuits. The invention dispenses with the conventional laser ablation process so as to simplify the fabrication process, save the fabrication cost and increase the product reliability.Type: GrantFiled: June 11, 2015Date of Patent: December 6, 2016Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Yan-Heng Chen, Mu-Hsuan Chan, Chieh-Yuan Chi, Chun-Tang Lin
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Patent number: 9397081Abstract: A semiconductor package is disclosed, which includes: a carrier having at least an opening; a plurality of conductive traces formed on the carrier and in the opening; a first semiconductor element disposed in the opening and electrically connected to the conductive traces; a second semiconductor element disposed on the first semiconductor element in the opening; and a redistribution layer structure formed on the carrier and the second semiconductor element for electrically connecting the conductive traces and the second semiconductor element. Since the semiconductor elements are embedded and therefore positioned in the opening of the carrier, the present invention eliminates the need to perform a molding process before forming the redistribution layer structure and prevents the semiconductor elements from displacement.Type: GrantFiled: October 2, 2015Date of Patent: July 19, 2016Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Yan-Heng Chen, Chun-Tang Lin, Yan-Yi Liao, Hung-Wen Liu, Chieh-Yuan Chi, Hsi-Chang Hsu
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Publication number: 20160141281Abstract: A semiconductor package is disclosed, which includes: a carrier having at least an opening; a plurality of conductive traces formed on the carrier and in the opening; a first semiconductor element disposed in the opening and electrically connected to the conductive traces; a second semiconductor element disposed on the first semiconductor element in the opening; and a redistribution layer structure formed on the carrier and the second semiconductor element for electrically connecting the conductive traces and the second semiconductor element. Since the semiconductor elements are embedded and therefore positioned in the opening of the carrier, the present invention eliminates the need to perform a molding process before forming the redistribution layer structure and prevents the semiconductor elements from displacement.Type: ApplicationFiled: October 2, 2015Publication date: May 19, 2016Inventors: Yan-Heng Chen, Chun-Tang Lin, Yan-Yi Liao, Hung-Wen Liu, Chieh-Yuan Chi, Hsi-Chang Hsu
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Patent number: 9337061Abstract: A fabrication method of a semiconductor package is disclosed, which includes the steps of: providing a carrier; disposing at least a semiconductor element on the carrier; forming an encapsulant on the carrier and the semiconductor element for encapsulating the semiconductor element; removing the carrier; disposing a pressure member on the encapsulant; and forming an RDL structure on the semiconductor element and the encapsulant, thereby suppressing internal stresses through the pressure member so as to mitigate warpage on edges of the encapsulant.Type: GrantFiled: January 9, 2014Date of Patent: May 10, 2016Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Yan-Heng Chen, Chun-Tang Lin, Mu-Hsuan Chan, Chieh-Yuan Chi, Yan-Yi Liao
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Publication number: 20160126126Abstract: A method for fabricating a package structure is provided, including the steps of: disposing on a carrier a semiconductor chip having an active surface facing the carrier; forming a patterned resist layer on the carrier; forming on the carrier an encapsulant exposing an inactive surface of the semiconductor chip and a surface of the patterned resist layer; and removing the carrier to obtain a package structure. Thereafter, redistribution layers can be formed on the opposite sides of the package structure, and a plurality of through holes can be formed in the patterned resist layer by drilling, thus allowing a plurality of conductive through holes to be formed in the through holes for electrically connecting the redistribution layers on the opposite sides of the package structure. Therefore, the invention overcomes the conventional drawback of surface roughness of the through holes caused by direct drilling the encapsulant having filler particles.Type: ApplicationFiled: August 26, 2015Publication date: May 5, 2016Inventors: Yan-Heng Chen, Chun-Tang Lin, Chieh-Yuan Chi
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Publication number: 20160111359Abstract: A method for fabricating an electronic package is provided, which includes the steps of: providing an insulating layer having at least an electronic element embedded therein; forming at least a first via hole on one side of the insulating layer; forming a first conductor in the first via hole of the insulating layer; forming on the insulating layer a first circuit structure electrically connected to the electronic element and the first conductor; and forming a second via hole on the other side of the insulating layer, wherein the second via hole communicates with the first via hole. As such, the second via hole and the first via hole constitute a through hole. Since the through hole is fabricated through two steps, the aspect ratio (depth/width) of the through hole can be adjusted according to the practical need so as to improve the process yield.Type: ApplicationFiled: September 23, 2015Publication date: April 21, 2016Inventors: Yan-Heng Chen, Chun-Tang Lin, Mu-Hsuan Chan, Chieh-Yuan Chi
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Publication number: 20160049376Abstract: A method for fabricating a package structure is provided, which includes the steps of: providing an encapsulant encapsulating at least an electronic element; forming a shaping layer on a surface of the encapsulant, wherein the shaping layer has at least an opening exposing a portion of the surface of the encapsulant; forming at least a through hole corresponding in position to the opening and penetrating the encapsulant; and forming a conductor in the through hole. The shaping layer facilitates to prevent deformation of the through hole.Type: ApplicationFiled: October 16, 2014Publication date: February 18, 2016Inventors: Yan-Heng Chen, Mu-Hsuan Chan, Chieh-Yuan Chi
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Publication number: 20160013146Abstract: A method for fabricating a package structure is provided, including the steps of: sequentially forming a metal layer and a dielectric layer on a first carrier, wherein the dielectric layer has a plurality of openings exposing portions of the metal layer; disposing an electronic element on the dielectric layer via an active surface thereof and mounting a plurality of conductive elements of metal balls on the exposed portions of the metal layer; forming an encapsulant on the dielectric layer for encapsulating the electronic element and the conductive elements; removing the first carrier; and patterning the metal layer into first circuits and forming second circuits on the dielectric layer, wherein the second circuits are electrically connected to the electronic element and the first circuits. The invention dispenses with the conventional laser ablation process so as to simplify the fabrication process, save the fabrication cost and increase the product reliability.Type: ApplicationFiled: June 11, 2015Publication date: January 14, 2016Inventors: Yan-Heng Chen, Mu-Hsuan Chan, Chieh-Yuan Chi, Chun-Tang Lin
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Patent number: 9224646Abstract: Disclosed is a method for fabricating a semiconductor package, including providing a package unit having an insulating layer and at least a semiconductor element embedded into the insulating layer, wherein the semiconductor element is exposed from the insulting layer and a plurality of recessed portions formed in the insulating layer; and electrically connecting a redistribution structure to the semiconductor element. The formation of the recessed portions release the stress of the insulating layer and prevent warpage of the insulating layer from taking place.Type: GrantFiled: January 2, 2014Date of Patent: December 29, 2015Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Yan-Heng Chen, Chun-Tang Lin, Chieh-Yuan Chi, Hung-Wen Liu
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Publication number: 20150325508Abstract: A carrier structure is provided, which includes: a metal oxide plate having opposite first and second surfaces and a plurality of through holes penetrating the first and second surfaces; a plurality of conductive portions formed in the through holes, respectively; and a plurality of conductive pads formed on the first surface of the metal oxide plate, wherein each of the conductive pads is correspondingly positioned on and in contact with a plurality of the conductive portions so as to be electrically connected to the plurality of the conductive portions. By replacing a conventional silicon interposer with the metal oxide plate, the present invention eliminates the need to form through silicon vias as required in the prior art and therefore simplifies the fabrication process.Type: ApplicationFiled: December 29, 2014Publication date: November 12, 2015Inventors: Yan-Heng Chen, Chung-Tang Lin, Chieh-Yuan Chi
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Patent number: 9177859Abstract: A semiconductor package is disclosed, which includes: a carrier having at least an opening; a plurality of conductive traces formed on the carrier and in the opening; a first semiconductor element disposed in the opening and electrically connected to the conductive traces; a second semiconductor element disposed on the first semiconductor element in the opening; and a redistribution layer structure formed on the carrier and the second semiconductor element for electrically connecting the conductive traces and the second semiconductor element. Since the semiconductor elements are embedded and therefore positioned in the opening of the carrier, the present invention eliminates the need to perform a molding process before forming the redistribution layer structure and prevents the semiconductor elements from displacement.Type: GrantFiled: August 29, 2013Date of Patent: November 3, 2015Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Yan-Heng Chen, Chun-Tang Lin, Yan-Yi Liao, Hung-Wen Liu, Chieh-Yuan Chi, Hsi-Chang Hsu
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Publication number: 20150294938Abstract: A method for fabricating a conductive via structure is provided, which includes the steps of: forming in an encapsulant a plurality of openings penetrating therethrough; forming a dielectric layer on the encapsulant and in the openings of the encapsulant; forming a plurality of vias in the dielectric layer in the openings of the encapsulant; and forming a conductive material in the vias to thereby form conductive vias. Therefore, by filling the openings having rough wall surfaces with the dielectric layer so as to form the vias having even wall surfaces, the present invention improves the quality of the conductive vias.Type: ApplicationFiled: March 26, 2015Publication date: October 15, 2015Inventors: Yan-Heng Chen, Chun-Tang Lin, Chieh-Yuan Chi, Mu-Hsuan Chan
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Publication number: 20140342506Abstract: Disclosed is a method for fabricating a semiconductor package, including providing a package unit having an insulating layer and at least a semiconductor element embedded into the insulating layer, wherein the semiconductor element is exposed from the insulting layer and a plurality of recessed portions formed in the insulating layer; and electrically connecting a redistribution structure to the semiconductor element. The formation of the recessed portions release the stress of the insulating layer and prevent warpage of the insulating layer from taking place.Type: ApplicationFiled: January 2, 2014Publication date: November 20, 2014Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTDInventors: Yan-Heng Chen, Chun-Tang Lin, Chieh-Yuan Chi, Hung-Wen Liu