Abstract: Disclosed is an open loop fractional frequency divider including an integer divider, a control circuit, and a phase interpolator. The integer divider processes an input clock according to the setting of a target frequency to generate a first frequency-divided clock and a second frequency-divided clock. The control circuit generates a coarse-tune control signal and a fine-tune control signal according to the setting. The phase interpolator generates an output clock according to the first frequency-divided clock, the second frequency-divided clock, and the two control signals. The two control signals are used for determining a first current, and their reversed signals are used for determining a second current. The phase interpolator controls a contribution of the first (second) frequency-divided clock to the generation of the output clock according to the first (second) frequency-divided clock, the reversed signal of the first (second) frequency-divided clock, and the first (second) current.

Abstract: Disclosed is an open loop fractional frequency divider including an integer divider, a control circuit, and a phase interpolator. The integer divider processes an input clock according to the setting of a target frequency to generate a first frequency-divided clock and a second frequency-divided clock. The control circuit generates a coarse-tune control signal and a fine-tune control signal according to the setting. The phase interpolator generates an output clock according to the first frequency-divided clock, the second frequency-divided clock, and the two control signals. The two control signals are used for determining a first current, and their reversed signals are used for determining a second current. The phase interpolator controls a contribution of the first (second) frequency-divided clock to the generation of the output clock according to the first (second) frequency-divided clock, the reversed signal of the first (second) frequency-divided clock, and the first (second) current.

Abstract: A multiprocessor system includes a first set of processors and a second set of processors. The first set of processors include a first set of standard cells and is configured to operate in a first frequency range. The second set of processors include a second set of standard cells and is configured to operate in a second frequency range. The first set of processors and the second set of processors have the same register-transfer level (RTL) description. Cells in the first set of standard cells have corresponding cells in the second set of standard cells with different characteristics. The first frequency range includes one or more frequencies higher than a maximum frequency in the second frequency range. The system also includes a clock generator that provides the same frequency to the first set of processors and the second set of processors.

Abstract: A multiprocessor system includes a first set of processors and a second set of processors. The first set of processors include a first set of standard cells and is configured to operate in a first frequency range. The second set of processors include a second set of standard cells and is configured to operate in a second frequency range. The first set of processors and the second set of processors have the same register-transfer level (RTL) description. Cells in the first set of standard cells have corresponding cells in the second set of standard cells with different characteristics. The first frequency range includes one or more frequencies higher than a maximum frequency in the second frequency range. The system also includes a clock generator that provides the same frequency to the first set of processors and the second set of processors.

Abstract: A data compression system and a data compression method using the same are provided. The data compression method includes acquiring original data from a memory and performs image processing and quantization on the original data to transform the original data into a quantization matrix. The data compression method then transforms the quantization matrix into a digital sequence based on a coding table and compares the data volume of the digital sequence and a target volume to generate a volume difference. The data compression method transforms the digital sequence into an inverse quantization matrix based on the volume difference and then transforms the inverse quantization matrix into a modified digital sequence based on the volume difference. The data compression method repeats the processes until the data volume of the digital sequence is substantially equal to a target volume or within an acceptable range of the target volume.

Abstract: A data compression system and a data compression method using the same are provided. The data compression method includes acquiring original data from a memory and performs image processing and quantization on the original data to transform the original data into a quantization matrix. The data compression method then transforms the quantization matrix into a digital sequence based on a coding table and compares the data volume of the digital sequence and a target volume to generate a volume difference. The data compression method transforms the digital sequence into an inverse quantization matrix based on the volume difference and then transforms the inverse quantization matrix into a modified digital sequence based on the volume difference. The data compression method repeats the processes until the data volume of the digital sequence is substantially equal to a target volume or within an acceptable range of the target volume.