Patents by Inventor Chieh-Yuan Lin

Chieh-Yuan Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11929767
    Abstract: A transmission interface between at least a first module and a second module is proposed. The transmission interface includes at least two physical transmission mediums. Each physical transmission medium is arranged to carry a multiplexed signal in which at least two signals are integrated. The at least two physical transmission mediums include a first physical transmission medium arranged to carry a first multiplexed signal including a first IF signal and a reference clock signal. The first IF signal and the reference clock signal are at different frequencies.
    Type: Grant
    Filed: August 16, 2022
    Date of Patent: March 12, 2024
    Assignee: MEDIATEK INC.
    Inventors: Chieh-Hsun Hsiao, Ming-Chou Wu, Wen-Chang Lee, Narayanan Baskaran, Wei-Hsin Tseng, Jenwei Ko, Po-Sen Tseng, Hsin-Hung Chen, Chih-Yuan Lin, Caiyi Wang
  • Publication number: 20070278701
    Abstract: A semiconductor package and a method for fabricating the same are disclosed. The method includes installing a plurality of conductive components on a plurality of chip carriers of a chip carrier module, connecting electrically the conductive components to electrical connection points of the adjacent chip carriers, mounting and electrically connecting a semiconductor chip to each of the chip carries, forming an encapsulant for enveloping the semiconductor chip and the conductive components, cutting the chip carriers to separate the conductive components installed thereon, exposing a portion of the conductive components out of the encapsulant, forming on the exposed portion of the conductive components an electroplated layer of nickel/gold, and separating the chip carriers from each other. The conductive components exposed out of the encapsulant provide extra electrical connection points and thereby promote the functionalities of electronic products.
    Type: Application
    Filed: November 1, 2006
    Publication date: December 6, 2007
    Applicant: Siliconware Precision Industries Co., Ltd.
    Inventors: Cheng-Yi Chang, Chien-Ping Huang, Chih-Ming Huang, Chieh-Yuan Lin, Cheng-Hsu Hsiao
  • Publication number: 20020146863
    Abstract: A modified SMT (Surface Mount Technology) process is proposed for mounting an exposed-pad type of semiconductor device over a PCB (printed circuit board), which can help prevent the problem of floated soldering of the semiconductor device over the PCB. By this modified SMT process, a plurality of via holes are formed in the pad-mounting area of the printed circuit board; and a solder material is pasted over the bottom end of each of the via holes. As the semiconductor device is mounted in position over the printed circuit board, a solder-reflow process is performed on the pasted solder material so as to cause the pasted solder material to be wetted to the entire surface of the solder-wettable layer in each of the via holes, thereby allowing the solder material to reflow to the upper end of each of the via holes where the reflowed solder is also wetted to the exposed die pad of the semiconductor device, thereby securely bonding the semiconductor device to the PCB.
    Type: Application
    Filed: April 10, 2001
    Publication date: October 10, 2002
    Inventors: Chieh-Yuan Lin, Jui-Yi Chuang, Chi-Chuan Wu
  • Patent number: 6455355
    Abstract: A modified SMT (Surface Mount Technology) process is proposed for mounting an exposed-pad type of semiconductor device over a PCB (printed circuit board), which can help prevent the problem of floated soldering of the semiconductor device over the PCB. By this modified SMT process, a plurality of via holes are formed in the pad-mounting area of the printed circuit board; and a solder material is pasted over the bottom end of each of the via holes. As the semiconductor device is mounted in position over the printed circuit board, a solder-reflow process is performed on the pasted solder material so as to cause the pasted solder material to be wetted to the entire surface of the solder-wettable layer in each of the via holes, thereby allowing the solder material to reflow to the upper end of each of the via holes where the reflowed solder is also wetted to the exposed die pad of the semiconductor device, thereby securely bonding the semiconductor device to the PCB.
    Type: Grant
    Filed: April 10, 2001
    Date of Patent: September 24, 2002
    Assignee: Siliconware Precision Industries, Co., Ltd.
    Inventors: Chieh-Yuan Lin, Jui-Yi Chuang, Chi-Chuan Wu