Patents by Inventor Chiemi Hashimoto

Chiemi Hashimoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11450731
    Abstract: A resistance element includes a conductor, the conductor having a repeating pattern of: a first conductive layer formed on a first interlayer insulating layer on a semiconductor substrate; a second conductive layer formed on a second interlayer insulating layer different from the first interlayer insulating layer; and an interlayer conductive layer connecting the first conductive layer and the second conductive layer, and the second conductive layer has a resistance-value fluctuation characteristic opposite to a resistance-value fluctuation characteristic of the first conductive layer after a heat treatment.
    Type: Grant
    Filed: January 21, 2021
    Date of Patent: September 20, 2022
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Chiemi Hashimoto, Kosuke Yayama, Hidekazu Tawara
  • Patent number: 11394371
    Abstract: The polysilicon resistance has a large resistance variation rate after the end of the mold packaging process. In order to enable high-precision trimming, it is desired to realize a resistance which is hardly affected by stress and temperature fluctuation generated in a substrate by a mold packaging process. A resistance element is formed in a plurality of wiring layers, and has a first conductive layer formed in a first wiring layer, a second conductive layer formed in a second wiring layer, and a repeating pattern of an interlayer conductive layer connecting the first conductive layer and the second conductive layer, and the interlayer conductive layer is formed of a plurality of types of materials.
    Type: Grant
    Filed: August 7, 2019
    Date of Patent: July 19, 2022
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Chiemi Hashimoto, Kosuke Yayama, Tomokazu Matsuzaki
  • Publication number: 20210257443
    Abstract: A resistance element includes a conductor, the conductor having a repeating pattern of: a first conductive layer formed on a first interlayer insulating layer on a semiconductor substrate; a second conductive layer formed on a second interlayer insulating layer different from the first interlayer insulating layer; and an interlayer conductive layer connecting the first conductive layer and the second conductive layer, and the second conductive layer has a resistance-value fluctuation characteristic opposite to a resistance-value fluctuation characteristic of the first conductive layer after a heat treatment.
    Type: Application
    Filed: January 21, 2021
    Publication date: August 19, 2021
    Inventors: Chiemi HASHIMOTO, Kosuke YAYAMA, Hidekazu TAWARA
  • Patent number: 10958250
    Abstract: A polycrystalline silicon resistor is large in coefficient of fluctuation in resistance between before and after the completion of a package molding process. To enable highly accurate trimming, it is desired to implement a resistor that is hardly subjected to stress produced in a substrate during a package molding process. A resistance element is formed of a plurality of wiring layers and has a repetitive pattern of a first conductive layer formed in a first wiring layer, a second conductive layer formed in a second wiring layer, and an interlayer conductive layer coupling the first conductive layer and the second conductive layer together.
    Type: Grant
    Filed: June 8, 2018
    Date of Patent: March 23, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Chiemi Hashimoto, Kosuke Yayama, Katsumi Tsuneno, Tomokazu Matsuzaki
  • Publication number: 20200076409
    Abstract: The polysilicon resistance has a large resistance variation rate after the end of the mold packaging process. In order to enable high-precision trimming, it is desired to realize a resistance which is hardly affected by stress and temperature fluctuation generated in a substrate by a mold packaging process. A resistance element is formed in a plurality of wiring layers, and has a first conductive layer formed in a first wiring layer, a second conductive layer formed in a second wiring layer, and a repeating pattern of an interlayer conductive layer connecting the first conductive layer and the second conductive layer, and the interlayer conductive layer is formed of a plurality of types of materials.
    Type: Application
    Filed: August 7, 2019
    Publication date: March 5, 2020
    Inventors: Chiemi HASHIMOTO, Kosuke YAYAMA, Tomokazu MATSUZAKI
  • Publication number: 20180375497
    Abstract: A polycrystalline silicon resistor is large in coefficient of fluctuation in resistance between before and after the completion of a package molding process. To enable highly accurate trimming, it is desired to implement a resistor that is hardly subjected to stress produced in a substrate during a package molding process. A resistance element is formed of a plurality of wiring layers and has a repetitive pattern of a first conductive layer formed in a first wiring layer, a second conductive layer formed in a second wiring layer, and an interlayer conductive layer coupling the first conductive layer and the second conductive layer together.
    Type: Application
    Filed: June 8, 2018
    Publication date: December 27, 2018
    Inventors: Chiemi HASHIMOTO, Kosuke YAYAMA, Katsumi TSUNENO, Tomokazu MATSUZAKI
  • Patent number: 8106478
    Abstract: A power source noise of a semiconductor device having a core cell configuring a logic circuit is reduced. Above the core cell configuring the logic circuit provided on a main surface of a semiconductor substrate are provided a first branch line for a first power source of the core cell, which is electrically connected to a first power source trunk line, and a second branch line for a second power source of the core cell, which is electrically connected to a second power source trunk line. The first and second branch lines are oppositely provided, thereby forming a capacitor between the first and second power sources.
    Type: Grant
    Filed: January 15, 2008
    Date of Patent: January 31, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Chiemi Hashimoto, Toshio Yamada
  • Publication number: 20080173914
    Abstract: A power source noise of a semiconductor device having a core cell configuring a logic circuit is reduced. Above the core cell configuring the logic circuit provided on a main surface of a semiconductor substrate are provided a first branch line for a first power source of the core cell, which is electrically connected to a first power source trunk line, and a second branch line for a second power source of the core cell, which is electrically connected to a second power source trunk line. The first and second branch lines are oppositely provided, thereby forming a capacitor between the first and second power sources.
    Type: Application
    Filed: January 15, 2008
    Publication date: July 24, 2008
    Inventors: Chiemi HASHIMOTO, Toshio Yamada
  • Publication number: 20040232464
    Abstract: Disclosed are a semiconductor integrated circuit device and a method of manufacturing the same capable of realizing the two-level gate insulator process for the DRAM without increasing the number of manufacturing steps and that of photomasks. After forming a gate electrode of a MISFET which constitutes a memory cell in a memory array region on a semiconductor substrate, the substrate is subjected to thermal treatment (re-oxidation process). At this time, since bird's beak of the thick gate insulating film formed below the sidewall portion of the gate electrode penetrates into the center of the gate electrode, a gate insulating film thicker than the gate insulating film before the re-oxidation process is formed just below the center of the gate electrode.
    Type: Application
    Filed: June 29, 2004
    Publication date: November 25, 2004
    Inventors: Chiemi Hashimoto, Yasuhiko Kawashima, Keizo Kawakita, Masahiro Moniwa, Hiroyasu Ishizuka, Akihiro Shimizu
  • Patent number: 6777279
    Abstract: Disclosed are a semiconductor integrated circuit device and a method of manufacturing the same capable of realizing the two-level gate insulator process for the DRAM without increasing the number of manufacturing steps and that of photomasks. After forming a gate electrode of a MISFET which constitutes a memory cell in a memory array region on a semiconductor substrate, the substrate is subjected to thermal treatment (re-oxidation process). At this time, since bird's beak of the thick gate insulating film formed below the sidewall portion of the gate electrode penetrates into the center of the gate electrode, a gate insulating film thicker than the gate insulating film before the re-oxidation process is formed just below the center of the gate electrode.
    Type: Grant
    Filed: April 14, 2003
    Date of Patent: August 17, 2004
    Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd., Elpida Memory, Inc.
    Inventors: Chiemi Hashimoto, Yasuhiko Kawashima, Keizo Kawakita, Masahiro Moniwa, Hiroyasu Ishizuka, Akihiro Shimizu
  • Publication number: 20030197202
    Abstract: Disclosed are a semiconductor integrated circuit device and a method of manufacturing the same capable of realizing the two-level gate insulator process for the DRAM without increasing the number of manufacturing steps and that of photomasks. After forming a gate electrode of a MISFET which constitutes a memory cell in a memory array region on a semiconductor substrate, the substrate is subjected to thermal treatment (re-oxidation process). At this time, since bird's beak of the thick gate insulating film formed below the sidewall portion of the gate electrode penetrates into the center of the gate electrode, a gate insulating film thicker than the gate insulating film before the re-oxidation process is formed just below the center of the gate electrode.
    Type: Application
    Filed: April 14, 2003
    Publication date: October 23, 2003
    Inventors: Chiemi Hashimoto, Yasuhiko Kawashima, Keizo Kawakita, Masahiro Moniwa, Hiroyasu Ishizuka, Akihiro Shimizu
  • Patent number: 5880497
    Abstract: A SRAM having its memory cell constructed to include transfer MISFETs to be controlled by word lines and a flip-flop circuit having driver MISFETs and load MISFETs. Plate electrodes of large area fixed on predetermined power source lines are arranged over the load MISFETs such that the plate electrodes over the offset region of the load MISFETs are formed with an opening. A silicon nitride film having a thickness permeable to hydrogen but not to humidity is formed over the transfer MISFETs and the driver MISFETs formed over the main surface of a semiconductor substrate and the load MISFETs formed of a polycrystalline silicon film deposited on the driver MISFETs.
    Type: Grant
    Filed: January 26, 1996
    Date of Patent: March 9, 1999
    Assignee: Hitachi, Ltd.
    Inventors: Shuji Ikeda, Koichi Imato, Kazuo Yoshizaki, Kohji Yamasaki, Soichiro Hashiba, Keiichi Yoshizumi, Yasuko Yoshida, Kousuke Okuyama, Mitsugu Oshima, Kazushi Tomita, Tsuyoshi Tabata, Kazushi Fukuda, Junichi Takano, Toshiaki Yamanaka, Chiemi Hashimoto, Motoko Kawashima, Fumiyuki Kanai, Takashi Hashimoto
  • Patent number: 5508540
    Abstract: A SRAM having its memory cell constructed to include transfer MISFETs to be controlled by word lines and a flip-flop circuit having driver MISFETs and load MISFETs. Plate electrodes of large area fixed on predetermined power source lines are arranged over the load MISFETs such that the plate electrodes over the offset region of the load MISFETs are formed with an opening. A silicon nitride film having a thickness permeable to hydrogen but not to humidity is formed over the transfer MISFETs and the driver MISFETs formed over the main surface of a semiconductor substrate and the load MISFETs formed of a polycrystalline silicon film deposited on the driver MISFETs.
    Type: Grant
    Filed: February 2, 1994
    Date of Patent: April 16, 1996
    Assignee: Hitachi, Ltd.
    Inventors: Shuji Ikeda, Koichi Imato, Kazuo Yoshizaki, Kohji Yamasaki, Soichiro Hashiba, Keiichi Yoshizumi, Yasuko Yoshida, Kousuke Okuyama, Mitsugu Oshima, Kazushi Tomita, Tsuyoshi Tabata, Kazushi Fukuda, Junichi Takano, Toshiaki Yamanaka, Chiemi Hashimoto, Motoko Kawashima, Fumiyuki Kanai, Takashi Hashimoto