Patents by Inventor Chien-An Liu

Chien-An Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • COMMUNICATION APPARATUS, ELECTRONIC APPARATUS AND ANTENNA ADJUSTMENT METHOD
    Publication number: 20190305414
    Abstract: A communication apparatus, an electronic apparatus and an antenna adjustment method thereof are provided. The communication apparatus includes an antenna system, a tuning portion and a switch circuit. The antenna system includes at least two antenna units. The tuning portion is disposed between the at least two antenna units and includes at least two branch units. The switch circuit is coupled to the tuning portion. The switch circuit switches a conduction from a first one of the branch units to a second one of the branch units according to a switching signal. The switching signal is related to performances of the antenna system. Accordingly, a dynamic and flexible adjustment mechanism can be provided to increase throughput and improve users' internet experience.
    Type: Application
    Filed: April 2, 2019
    Publication date: October 3, 2019
    Applicant: COMPAL ELECTRONICS, INC.
    Inventors: Liang-Che Chou, Li-Chun Lee, Yu-Chun Hsieh, Mau-Chi Sun, Jui-Hung Lai, Wen-Feng Tsai, Chih-Chien Liu
  • SEMICONDUCTOR STRUCTURE WITH A CONDUCTIVE LINE AND FABRICATING METHOD OF A STOP LAYER
    Publication number: 20190287976
    Abstract: A fabricating method of a stop layer includes providing a substrate. The substrate is divided into a memory region and a peripheral circuit region. Two conductive lines are disposed within the peripheral circuit region. Then, an atomic layer deposition is performed to form a silicon nitride layer to cover the conductive lines. Later, after forming the silicon nitride layer, a silicon carbon nitride layer is formed to cover the silicon nitride layer. The silicon carbon nitride layer serves as a stop layer.
    Type: Application
    Filed: April 23, 2018
    Publication date: September 19, 2019
    Inventors: Chih-Chien Liu, Tzu-Chin Wu, Po-Chun Chen, Chia-Lung Chang
  • MAGNETIC TUNNEL JUNCTION STRUCTURE OF MAGNETIC RANDOM ACCESS MEMORY CELL
    Publication number: 20190259762
    Abstract: A magnetic tunnel junction (MTJ) structure of a magnetic random access memory (MRAM) cell includes an insulation layer, a patterned MTJ film stack, an aluminum oxide protection layer, an interlayer dielectric, and a connection structure. The patterned MTJ film stack is disposed on the insulation layer. The aluminum oxide protection layer is disposed on a sidewall of the patterned MTJ film stack, and the aluminum oxide protection layer includes an aluminum film oxidized by an oxidation treatment. The interlayer dielectric covers the aluminum oxide protection layer and the patterned MTJ film stack. The connection structure penetrates the interlayer dielectric above the patterned MTJ film stack, and the connection structure is electrically connected to a topmost portion of the patterned MTJ film stack.
    Type: Application
    Filed: May 2, 2019
    Publication date: August 22, 2019
    Inventors: Hsiao-Pang Chou, Yu-Ru Yang, Chih-Chien Liu, Chao-Ching Hsieh, Chun-Hsien Lin
  • SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME
    Publication number: 20190249297
    Abstract: A semiconductor device includes a substrate, a dielectric layer, a first tungsten layer, an interface layer and a second tungsten layer. The dielectric layer is disposed on the substrate and has a first opening and a second opening larger than the first opening. The first tungsten layer is filled in the first opening and is disposed in the second opening. The second tungsten layer is disposed on the first tungsten layer in the second opening, wherein the second tungsten layer has a grain size gradually increased from a bottom surface to a top surface. The interface layer is disposed between the first tungsten layer and the second tungsten layer, wherein the interface layer comprises a nitrogen containing layer. The present invention further includes a method of forming a semiconductor device.
    Type: Application
    Filed: March 12, 2018
    Publication date: August 15, 2019
    Inventors: Chih-Chien Liu, Pin-Hong Chen, Tsun-Min Cheng, Yi-Wei Chen
  • Epitaxial process applying light illumination
    Patent number: 10381228
    Abstract: An epitaxial process applying light illumination includes the following steps. A substrate is provided. A dry etching process and a wet etching process are performed to form a recess in the substrate, wherein an infrared light illuminates while the wet etching process is performed. An epitaxial structure is formed in the recess.
    Type: Grant
    Filed: February 25, 2015
    Date of Patent: August 13, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yu-Ying Lin, Ted Ming-Lang Guo, Chin-Cheng Chien, Chih-Chien Liu, Hsin-Kuo Hsu, Chin-Fu Lin, Chun-Yuan Wu
  • Method for fabricating semiconductor device
    Patent number: 10374051
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a silicon layer on a substrate; forming a metal silicon nitride layer on the silicon layer; forming a stress layer on the metal silicon nitride layer; performing a thermal treatment process; removing the stress layer; forming a conductive layer on the metal silicon nitride layer; and patterning the conductive layer, the metal silicon nitride layer, and the silicon layer to form a gate structure.
    Type: Grant
    Filed: May 23, 2018
    Date of Patent: August 6, 2019
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Ji-Min Lin, Yi-Wei Chen, Tsun-Min Cheng, Pin-Hong Chen, Chih-Chien Liu, Chun-Chieh Chiu, Tzu-Chieh Chen, Chih-Chieh Tsai, Yi-An Huang, Kai-Jiun Chang
  • SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
    Publication number: 20190221570
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a bit line structure on a substrate; forming a first spacer, a second spacer, and a third spacer around the bit line structure; forming an interlayer dielectric (ILD) layer on the bit line structure; planarizing part of the ILD layer; removing the ILD layer and the second spacer to form a recess between the first spacer and the third spacer; and forming a liner in the recess.
    Type: Application
    Filed: February 14, 2018
    Publication date: July 18, 2019
    Inventors: Chih-Chien Liu, Chia-Lung Chang, Tzu-Chin Wu, Wei-Lun Hsu
  • Camera device, video auto-tagging method and non-transitory computer readable medium thereof
    Patent number: 10356312
    Abstract: A camera device, a video auto-tagging method and a non-transitory computer readable medium thereof are provided. The camera device comprises a processor, a camera and a sensor module. The camera is configured to capture a video. The sensor module is configured to generate distinctive sensing information after sensing a distinctive motion event of an user. The processor is configured to create a timing tag for the video according to the distinctive sensing information.
    Type: Grant
    Filed: March 27, 2014
    Date of Patent: July 16, 2019
    Assignee: HTC CORPORATION
    Inventors: Yuan-Mao Tsui, Yuan-Kang Wang, Wen-Chien Liu
  • Memory devices and method of manufacturing the same
    Patent number: 10332888
    Abstract: A method of manufacturing memory devices is provided in the present invention. The method includes the steps of providing a substrate with multiple capacitors, wherein the capacitor includes a lower electrode layer, an insulating layer and an upper electrode layer and a top plate, forming a tungsten layer on the upper electrode, performing a nitriding plasma treatment to the tungsten layer to form a tungsten nitride layer, and forming a pre-metal dielectric layer on the tungsten nitride layer.
    Type: Grant
    Filed: November 13, 2017
    Date of Patent: June 25, 2019
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Chih-Chien Liu, Chia-Lung Chang, Han-Yung Tsai, Tzu-Chin Wu
  • Manufacturing method of magnetic random access memory cell
    Patent number: 10312238
    Abstract: A manufacturing method of a magnetic random access memory (MRAM) cell includes the following steps. A magnetic tunnel junction (MTJ) film stack is formed on an insulation layer. An aluminum mask layer is formed on the MTJ film stack. A hard mask layer is formed on the aluminum mask layer. An ion beam etching (IBE) process is performed with the aluminum mask layer and the hard mask layer as a mask. The MTJ film stack is patterned to be a patterned MTJ film stack by the IBE process, and at least apart of the aluminum mask layer is bombarded by the IBE process for forming an aluminum film on a sidewall of the patterned MTJ film stack. An oxidation treatment is performed, and the aluminum film is oxidized to be an aluminum oxide protection layer on the sidewall of the patterned MTJ film stack by the oxidation treatment.
    Type: Grant
    Filed: November 6, 2017
    Date of Patent: June 4, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hsiao-Pang Chou, Yu-Ru Yang, Chih-Chien Liu, Chao-Ching Hsieh, Chun-Hsien Lin
  • MEMORY DEVICES AND METHOD OF MANUFACTURING THE SAME
    Publication number: 20190148382
    Abstract: A method of manufacturing memory devices is provided in the present invention. The method includes the steps of providing a substrate with multiple capacitors, wherein the capacitor includes a lower electrode layer, an insulating layer and an upper electrode layer and a top plate, forming a tungsten layer on the upper electrode, performing a nitriding plasma treatment to the tungsten layer to form a tungsten nitride layer, and forming a pre-metal dielectric layer on the tungsten nitride layer.
    Type: Application
    Filed: November 13, 2017
    Publication date: May 16, 2019
    Inventors: Chih-Chien Liu, Chia-Lung Chang, Han-Yung Tsai, Tzu-Chin Wu
  • MANUFACTURING METHOD OF MAGNETIC RANDOM ACCESS MEMORY CELL
    Publication number: 20190139959
    Abstract: A manufacturing method of a magnetic random access memory (MRAM) cell includes the following steps. A magnetic tunnel junction (MTJ) film stack is formed on an insulation layer. An aluminum mask layer is formed on the MTJ film stack. A hard mask layer is formed on the aluminum mask layer. An ion beam etching (IBE) process is performed with the aluminum mask layer and the hard mask layer as a mask. The MTJ film stack is patterned to be a patterned MTJ film stack by the IBE process, and at least apart of the aluminum mask layer is bombarded by the IBE process for forming an aluminum film on a sidewall of the patterned MTJ film stack. An oxidation treatment is performed, and the aluminum film is oxidized to be an aluminum oxide protection layer on the sidewall of the patterned MTJ film stack by the oxidation treatment.
    Type: Application
    Filed: November 6, 2017
    Publication date: May 9, 2019
    Inventors: Hsiao-Pang Chou, Yu-Ru Yang, Chih-Chien Liu, Chao-Ching Hsieh, Chun-Hsien Lin
  • Semiconductor structure and the method of making the same
    Patent number: 10283564
    Abstract: The present invention provides a semiconductor structure, the semiconductor structure includes a substrate comprising a diffusion region, a transistor structure on the substrate, and a resistive random access memory (RRAM) on the substrate, wherein the resistive random access memory includes at least one metal silicide layer in direct contact with the diffusion region, and a lower electrode, a resistive switching layer and an upper electrode are sequentially disposed on the metal silicide layer.
    Type: Grant
    Filed: November 8, 2017
    Date of Patent: May 7, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Chien Liu, Chao-Ching Hsieh, Yu-Ru Yang, Hsiao-Pang Chou
  • Semiconductor device and method for fabricating the same
    Patent number: 10276389
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a silicon layer on a substrate; forming a first metal silicon nitride layer on the silicon layer; performing an oxygen treatment process to form an oxide layer on the first metal silicon nitride layer; forming a second metal silicon nitride layer on the oxide layer; forming a conductive layer on the second metal silicon nitride layer; and patterning the conductive layer, the second metal silicon nitride layer, the oxide layer, the first metal silicon nitride layer, and the silicon layer to form a gate structure.
    Type: Grant
    Filed: May 23, 2018
    Date of Patent: April 30, 2019
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Chih-Chieh Tsai, Yi-Wei Chen, Pin-Hong Chen, Chih-Chien Liu, Tzu-Chieh Chen, Chun-Chieh Chiu, Tsun-Min Cheng, Kai-Jiun Chang, Chia-Chen Wu, Yi-An Huang
  • SEMICONDUCTOR STRUCTURE AND THE METHOD OF MAKING THE SAME
    Publication number: 20190123104
    Abstract: The present invention provides a semiconductor structure, the semiconductor structure includes a fin transistor (fin filed effect transistor, finFET) located on a substrate, the fin transistor includes a gate structure crossing over a fin structure, and at least one source/drain region. And a resistive random access memory (RRAM) includes a lower electrode, a resistance switching layer and a top electrode being sequentially located on the source/drain region and electrically connected to the fin transistor.
    Type: Application
    Filed: November 20, 2017
    Publication date: April 25, 2019
    Inventors: Yu-Ru Yang, Chih-Chien Liu, Chao-Ching Hsieh, Hsiao-Pang Chou
  • Semiconductor structure and the method of making the same
    Patent number: 10269868
    Abstract: The present invention provides a semiconductor structure, the semiconductor structure includes a fin transistor (fin filed effect transistor, finFET) located on a substrate, the fin transistor includes a gate structure crossing over a fin structure, and at least one source/drain region. And a resistive random access memory (RRAM) includes a lower electrode, a resistance switching layer and a top electrode being sequentially located on the source/drain region and electrically connected to the fin transistor.
    Type: Grant
    Filed: November 20, 2017
    Date of Patent: April 23, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yu-Ru Yang, Chih-Chien Liu, Chao-Ching Hsieh, Hsiao-Pang Chou
  • SEMICONDUCTOR STRUCTURE AND THE METHOD OF MAKING THE SAME
    Publication number: 20190115394
    Abstract: The present invention provides a semiconductor structure, the semiconductor structure includes a substrate comprising a diffusion region, a transistor structure on the substrate, and a resistive random access memory (RRAM) on the substrate, wherein the resistive random access memory includes at least one metal silicide layer in direct contact with the diffusion region, and a lower electrode, a resistive switching layer and an upper electrode are sequentially disposed on the metal silicide layer.
    Type: Application
    Filed: November 8, 2017
    Publication date: April 18, 2019
    Inventors: Chih-Chien Liu, Chao-Ching Hsieh, Yu-Ru Yang, Hsiao-Pang Chou
  • METHOD FOR ROLE-BASED DATA TRANSMISSION USING PHYSICALLY UNCLONABLE FUNCTION (PUF)-BASED KEYS
    Publication number: 20190116028
    Abstract: A method includes encrypting a first message that contains a first public key of a first peer, by using a second public key of a second peer, and decrypting a second message sent from the second peer by using a first private key paired with the first public key. The second message is encrypted at the second peer by using the first public key, and contains an encrypted data encrypted by using the second public key and hashed by using a secret key of the first peer.
    Type: Application
    Filed: March 27, 2018
    Publication date: April 18, 2019
    Inventor: MEI-CHIEN LIU
  • MOTION DETECTING DEVICE AND DETECTING METHOD FOR REPETITIVE MOTION
    Publication number: 20190079109
    Abstract: A detecting method for repetitive motion includes receiving a plurality of accelerated velocities, receiving a plurality of angular velocities, determining a plurality of stationary points according to the accelerated velocities, determining a plurality of motion periods according to the stationary points, wherein the motion periods separately correspond to different sets of the angular velocities, and clustering the motion periods according to differences among the different sets of angular velocities corresponding to the motion periods.
    Type: Application
    Filed: November 12, 2018
    Publication date: March 14, 2019
    Inventors: Jiaw-Chang WANG, I-Chien LIU, Shih-Yen KU
  • METHOD AND SYSTEM FOR PERFORMING VIRTUAL-REALITY-BASED ASSESSMENT OF MENTAL AND BEHAVIORAL CONDITION
    Publication number: 20190066383
    Abstract: A method for performing an assessment of mental and behavioral condition of a subject includes displaying, by a virtual reality (VR) device, a VR scene; generating, by the VR device, a notification indicating an assignment for the subject in the VR scene; recording, by a recording device, a response of the subject to the assignment; calculating, by a processing device, at least one score based on the response; and comparing, by the processing device, the score with a pre-established normative scale to generate an assessment result for the mental and behavioral condition of the subject.
    Type: Application
    Filed: August 13, 2018
    Publication date: February 28, 2019
    Applicant: National Taiwan Normal University
    Inventors: Tzu-Chien LIU, Li-Yu HUNG, Yu-Chen KUO