Abstract: An integrated circuit (IC) with conductive structures and a method of fabricating the IC are disclosed. The method includes depositing a first dielectric layer on a semiconductor device, forming a conductive structure in the first dielectric layer, removing a portion of the first dielectric layer to expose a sidewall of the conductive structure, forming a barrier structure surrounding the sidewall of the conductive structure, depositing a conductive layer on the barrier structure, and performing a polishing process on the barrier structure and the conductive layer.

Abstract: A transistor structure including a substrate, a gate structure, a first doped region, a second doped region, a drift region, a field plate, a charge storage layer, and a first dielectric layer is provided. The gate structure is located on the substrate. The first doped region and the second doped region are located in the substrate on two sides of the gate structure. The drift region is located in the substrate between the gate structure and the second doped region. The field plate is located on the substrate above the drift region. The charge storage layer is located between the field plate and the drift region. The first dielectric layer is located between the field plate and the charge storage layer.

Abstract: A nano-FET and a method of forming is provided. In some embodiments, a nano-FET includes an epitaxial source/drain region contacting ends of a first nanostructure and a second nanostructure. The epitaxial source/drain region may include a first semiconductor material layer of a first semiconductor material, such that the first semiconductor material layer includes a first segment contacting the first nanostructure and a second segment contacting the second nanostructure, wherein the first segment is separated from the second segment. A second semiconductor material layer is formed over the first segment and the second segment. The second semiconductor material layer may include a second semiconductor material having a higher concentration of dopants of a first conductivity type than the first semiconductor material layer. The second semiconductor material layer may have a lower concentration percentage of silicon than the first semiconductor material layer.

Abstract: An image capturing assembly including a mounting base, a driving component, a first gear, a second gear, a lens assembly, a third gear and a resistance component. The driving component is disposed on the mounting base. The first gear is connected to the driving component and configured to be driven by the driving component. The second gear is pivotally connected to the mounting base and connected to the first gear. The driving component is configured to drive the second gear via the first gear. The lens assembly is fixed to the second gear. The third gear is pivotally connected to the mounting base and engaged with the second gear. The resistance component presses against the third gear to allow the third gear to transmit a resistance against the second gear during a rotation of the second gear.

Abstract: Semiconductor structures and fabrication methods are provided. In one example, a method includes forming a first dielectric layer on a semiconductor structure. The semiconductor structure includes a substrate and a multi-layer interconnect (MLI) structure on the substrate. The MLI structure includes multiple metallization layers. The first dielectric layer is formed on a topmost metallization layer. The method further includes forming a through-substrate-via (TSV) opening extending vertically through the first dielectric layer and the multiple metallization layers into the substrate, forming a TSV in the TSV opening, performing a first planarization process to planarize the TSV, forming multiple first metal vias and first metal lines in the first dielectric layer after the first planarization process, forming multiple first metal capping layers respectively on the multiple first metal lines, and performing a second planarization process to planarize the first metal capping layers.

Abstract: A liquid reservoir includes a liquid storage chamber, a nebulizing module, a detection module, a lid, and a bubble blocking structure. The liquid storage chamber has an opening, and a bottom of the liquid storage chamber has a through hole. The nebulizing module is disposed in the through hole. The detection module is disposed within the liquid storage chamber and adjacent to the through hole. The lid is disposed on the liquid storage chamber and covers the opening. The bubble blocking structure is disposed in the liquid storage chamber, and an orthogonal projection of the bubble blocking structure that is projected to the bottom of the liquid storage chamber at least partially overlaps with the through hole.

Abstract: Semiconductor structures, die stack structures, and fabrication methods are provided. In one example, a semiconductor structure includes a die having a test pad disposed on a front side of the die. The test pad has a probe mark in an upper portion of the test pad. The probe mark has an open end at a top surface of the test pad, a bottom wall, a sidewall connected to the bottom wall, and a space between the open end, the bottom wall and the sidewall. The semiconductor structure further includes a first cover layer and a second cover layer. The first cover layer is disposed on the front side of the first test pad and the sidewall and the bottom wall of the probe mark. The second cover layer is disposed on the first cover layer. The first and second cover layers comprise different materials.

Abstract: An embodiment is a structure including a first fin over a substrate, a second fin over the substrate, the second fin being adjacent the first fin, an isolation region surrounding the first fin and the second fin, a gate structure along sidewalls and over upper surfaces of the first fin and the second fin, the gate structure defining channel regions in the first fin and the second fin, a source/drain region on the first fin and the second fin adjacent the gate structure, and an air gap separating the source/drain region from a top surface of the substrate.

Abstract: A game controller configured for a mobile device. The game controller includes a connection mechanism, two control handles, and at least one first pad. The control handles are respectively coupled to two opposite sides of the connection mechanism. Each of the two control handles has an accommodation recess, and the two accommodation recesses of the two control handles are configured to accommodate the mobile device. The first pad is removably disposed on one of the two control handles and located in the accommodation recess of the one of the two control handles, and the at least one first pad is configured to be located between and clamped by the mobile device and the one of the two control handles.

Abstract: A display device includes a backlight assembly that emits blue light, and a mold frame with a portion that is coated with a yellow phosphor. Some of the blue light emitted by the backlight assembly strikes the portion of the mold frame and combines with yellow light from the yellow phosphor to produce a white light.

Abstract: A method of using a coupling system includes aligning an optical fiber with a cavity in a chip, wherein aligning the optical fiber comprises orienting the fiber within an angle ranging from about 88-degrees to about 92-degrees with respect to a top surface of the chip. The method further includes emitting an optical signal from the optical fiber. The method further includes redirecting the optical signal into a waveguide using a grating positioned on an opposite side of the cavity from the optical fiber.

Abstract: A casing of an oven includes a base, two first plates and two second plates. The base has two first pivot portions and two second pivot portions. Two first axes and two second axes are defined. Each of the two first axes passes through one of the two first pivot portions. Each of the two second axes passes through one of the two second pivot portions. Each of the two first axes and the two second axes re spaced apart from one another in a height direction of the base. Each of the two first plates is pivotally connected to one of the two first pivot portions. Each of the two second plates is pivotally connected to one of the two second pivot portions. As the four axes are respectively located at different positions in the height direction of the base, the two first plates could be stacked and the two second plates could be stacked upon folding the casing.

Abstract: Semiconductor devices and methods of manufacturing are provided. In some embodiments the method includes depositing an etch stop layer over a first hard mask material, the first hard mask material over a gate stack, depositing an interlayer dielectric over the etch stop layer, forming a first opening through the interlayer dielectric, the etch stop layer, and the first hard mask material, the first opening exposing a conductive portion of the gate stack, and treating sidewalls of the first opening with a first dopant to form a first treated region within the interlayer dielectric, a second treated region within the etch stop layer, a third treated region within the first hard mask material, and a fourth treated region within the conductive portion, wherein after the treating the fourth treated region has a higher concentration of the first dopant than the first treated region.

Abstract: A package comprises an interposer, comprising an interposer substrate including at least one layer, and a plurality of RDLs formed through at least a portion of the interposer substrate. The package also includes a die device structure comprising at least one device die, and a first test line (TL) structure interposed between the interposer and the die device structure. The first TL structure includes at least one first test line electrically coupled to the at least one device die, at least a portion of the at least one first test line extending beyond a peripheral edge of the die device structure to provide an electrical interface with the at least one device die.

Abstract: A method of making a photonic device includes depositing a cladding layer over a silicon layer. The method further includes patterning the cladding layer to expose a first portion of the silicon layer, wherein a second portion of the silicon layer is covered by the patterned cladding layer, and a waveguide portion is in the second portion of the silicon layer. The method further includes depositing a low refractive index layer directly over the patterned cladding layer, wherein a refractive index of the low refractive index layer is less than a refractive index of silicon nitride.

Abstract: A three-dimensional device structure includes a die including a semiconductor substrate, an interconnect structure disposed on the semiconductor substrate, a through silicon via (TSV) structure that extends through the semiconductor substrate and electrically contacts a metal feature of the interconnect structure, and an integrated passive device (IPD) embedded in the semiconductor substrate and electrically connected to the TSV structure.

Abstract: A barrier layer is formed in a portion of a thickness of sidewalls in a recess prior to formation of an interconnect structure in the recess. The barrier layer is formed in the portion of the thickness of the sidewalls by a plasma-based deposition operation, in which a precursor reacts with a silicon-rich surface to form the barrier layer. The barrier layer is formed in the portion of the thickness of the sidewalls in that the precursor consumes a portion of the silicon-rich surface of the sidewalls as a result of the plasma treatment. This enables the barrier layer to be formed in a manner in which the cross-sectional width reduction in the recess from the barrier layer is minimized while enabling the barrier layer to be used to promote adhesion in the recess.

Abstract: A semiconductor structure includes a core layer; a passive component disposed within the core layer; and a first redistribution layer disposed over the core layer, wherein the first redistribution layer includes a first interconnect, a second interconnect, and a third interconnect disposed between and electrically isolated from the first interconnect and the second interconnect. The third interconnect is electrically connected to the passive component, and at least one of the first interconnect and the second interconnect is electrically isolated from the passive component. A method of manufacturing the semiconductor structure includes providing a first bias between the first interconnect and the second interconnect, providing a second bias to the passive component through the third interconnect, wherein the first bias is greater than the second bias.

Abstract: A coupling system includes an optical fiber configured to carry an optical signal. The coupling system further includes a grating on a first side of a semiconductor layer, wherein the grating is configured to receive the optical signal. The coupling system further includes an interconnect structure over the grating on the first side of the semiconductor layer, wherein the interconnect structure defines a cavity aligned with the grating. The coupling system further includes a first polysilicon layer on a second side of the semiconductor layer, wherein the second side of the semiconductor layer is opposite to the first side of the semiconductor layer.