Abstract: A semiconductor device includes a gate structure on a substrate and a dielectric film stack over the gate structure and the substrate, where the dielectric film stack includes a first inter layer dielectric (ILD) over the substrate and the gate structure, a barrier layer over the first ILD, a second ILD over the barrier layer, and a contact extending through the dielectric film stack. An upper portion of a contact sidewall has a first slope, a lower portion of the contact sidewall has a second slope different from the first slope, and a transition from the first slope to the second slope occurs at a portion of the contact extending through the barrier layer.

Abstract: Methods for making semiconductor device having improve contact structures including the operations of depositing a first dielectric material, depositing a barrier material over the first dielectric material, depositing a second dielectric material over the barrier material, etching a two-slope contact opening with an upper sidewall angle of the opening through the second dielectric material that is less than a lower sidewall angle of the opening through the first dielectric material, and filling the two-slope contact opening with a conductive material, the conductive material.

Abstract: A semiconductor device includes a gate structure on a substrate and a dielectric film stack over the gate structure and the substrate, where the dielectric film stack includes a first inter layer dielectric (ILD) over the substrate and the gate structure, a barrier layer over the first ILD, a second ILD over the barrier layer, and a contact extending through the dielectric film stack. An upper portion of a contact sidewall has a first slope, a lower portion of the contact sidewall has a second slope different from the first slope, and a transition from the first slope to the second slope occurs at a portion of the contact extending through the barrier layer.

Abstract: A method of forming a shallow trench isolation (STI) structure in a substrate includes forming a pad oxide layer over the substrate. The method includes forming a nitride-containing layer over the pad oxide layer, wherein the nitride-containing layer has a first thickness. The method further includes forming the STI structure extending through the nitride-containing layer, into the substrate. The STI structure has a height above a top surface of the pad oxide layer. The method includes establishing a correlation between the first thickness, the height of the STI structure above the top surface of the pad oxide layer, and an offset between the first thickness and the height of the STI structure above the top surface of the pad oxide layer. The method includes calculating the height of the STI structure above the pad oxide layer based on the correlation, and selectively removing a determined thickness of the STI structure.

Abstract: A method of forming a shallow trench isolation (STI) structure in a substrate includes forming a pad oxide layer over the substrate. The method includes forming a nitride-containing layer over the pad oxide layer, wherein the nitride-containing layer has a first thickness. The method further includes forming the STI structure extending through the nitride-containing layer, into the substrate. The STI structure has a height above a top surface of the pad oxide layer. The method includes establishing a correlation between the first thickness, the height of the STI structure above the top surface of the pad oxide layer, and an offset between the first thickness and the height of the STI structure above the top surface of the pad oxide layer. The method includes calculating the height of the STI structure above the pad oxide layer based on the correlation, and selectively removing a determined thickness of the STI structure.

Abstract: A method for forming a shallow trench isolation (STI) structure with a predetermined target height is provided. A substrate having a pad oxide layer formed on the substrate is provided. A nitride-containing layer with a thickness is formed on the pad oxide. A STI structure is formed and extends through the nitride-containing layer, the pad oxide layer, into the substrate. The thickness of the nitride-containing layer is measured to calculate the height of STI structure according to a correlation between the thickness of the nitride-containing layer and the height of STI structure. A thickness of the top portion STI structure to be removed is determined according to the difference between the height of the STI structure and the predetermined target height and is removed in a first etching process. The nitride-containing layer is removed without etching the STI structure or the pad oxide layer in a second etching process.

Abstract: A semiconductor device includes a spacer adjacent a gate structure. A protection layer covers oxide portions of the spacer surface such that subsequent manufacturing operations such as wet oxide etches and strips, do not produce voids in the spacers. A method for forming the semiconductor device provides forming a gate structure with adjacent spacers including an oxide liner beneath a nitride section, then forming the protection layer over the structure, and removing portions of the protection layer but leaving other portions of the protection layer intact to cover and protect underlying oxide portions of the spacer during subsequent processing such as the formation and removal of a resist protect oxide (RPO) layer. The protection layer is advantageously formed of a nitride film and an oxide film and produces a double spacer effect when partially removed such that only vertical sections remain.

Abstract: Provided is a semiconductor interconnect structure formed from an original damascene or dual damascene structure. The original damascene or dual damascene structure includes a planar upper surface consisting of planar upper surfaces of conductive structures formed within openings formed in the dielectric, and planar upper surfaces of the dielectric. The original structure is processed using wet or dry etching operations which, by including ion bombardment and/or ion milling characteristics, both etch the upper dielectric surface and round the upper edges of the originally formed interconnect structures that become exposed as the dielectric is etched. Produced is an interconnect structure within an opening formed in a dielectric and which includes an upper portion that extends above the dielectric and includes opposed upper edges that are rounded.