Patents by Inventor Chien-Chang Tseng

Chien-Chang Tseng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11960381
    Abstract: A memory check method, a memory check device and a memory check system are disclosed. The method includes the following. A debug file is generated according to a source code, where the debug file carries symbol information related to a description message in the source code. Memory data generated by a memory storage device in execution of a firmware is received. The debug file is loaded to automatically analyze the memory data. In addition, an analysis result is presented by an application program interface, where the analysis result reflects a status of the firmware with assistance of the symbol information.
    Type: Grant
    Filed: March 15, 2021
    Date of Patent: April 16, 2024
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Chien Chang Tseng
  • Publication number: 20220306425
    Abstract: A double drawcord winding device has a belt pulley supported by a belt pulley bearing to mount on a webbing wheel shaft, two one-way bearings disposed on two sides of the belt pulley bearing, a second shaft sleeve securely mounted on the belt pulley and mounted around the one-way bearings, two winding devices disposed on two sides of the belt pulley and each having a first shaft sleeve extended toward the belt pulley, inserted into and mounted in one of the one-way bearings, each winding device having a winding bearing, a pull cord and a coil spring with two ends, two locating sleeves mounted on the webbing wheel shaft and mounted in the winding devices, one of the two ends of the coil spring connected to the locating sleeve, and other end connected to the winding device.
    Type: Application
    Filed: March 18, 2022
    Publication date: September 29, 2022
    Inventor: CHIEN CHANG TSENG
  • Publication number: 20220269581
    Abstract: A memory check method, a memory check device and a memory check system are disclosed. The method includes the following. A debug file is generated according to a source code, where the debug file carries symbol information related to a description message in the source code. Memory data generated by a memory storage device in execution of a firmware is received. The debug file is loaded to automatically analyze the memory data. In addition, an analysis result is presented by an application program interface, where the analysis result reflects a status of the firmware with assistance of the symbol information.
    Type: Application
    Filed: March 15, 2021
    Publication date: August 25, 2022
    Applicant: PHISON ELECTRONICS CORP.
    Inventor: Chien Chang Tseng
  • Patent number: 9741313
    Abstract: A gate driving circuit includes a shift register circuit and an auxiliary circuit which are disposed at different sides of a pixel array. The shift register circuit includes an (N?1)th shift register stage for generating an (N?1)th gate signal according to a first clock, an Nth shift register stage for generating an Nth gate signal according to a second clock, and an (N+1)th shift register stage for generating an (N+1)th gate signal according to a third clock. The auxiliary circuit includes a first transistor. The first transistor performs the signal voltage stabilization and level switching acceleration operations on the Nth gate signal according to the (N?1)th gate signal and the second clock.
    Type: Grant
    Filed: July 30, 2015
    Date of Patent: August 22, 2017
    Assignee: AU OPTRONICS CORP.
    Inventors: Chien-Chang Tseng, Kuang-Hsiang Liu, Ya-Ting Yang
  • Publication number: 20150332652
    Abstract: A gate driving circuit includes a shift register circuit and an auxiliary circuit which are disposed at different sides of a pixel array. The shift register circuit includes an (N?1)th shift register stage for generating an (N?1)th gate signal according to a first clock, an Nth shift register stage for generating an Nth gate signal according to a second clock, and an (N+1)th shift register stage for generating an (N+1)th gate signal according to a third clock. The auxiliary circuit includes a first transistor. The first transistor performs the signal voltage stabilization and level switching acceleration operations on the Nth gate signal according to the (N?1)th gate signal and the second clock.
    Type: Application
    Filed: July 30, 2015
    Publication date: November 19, 2015
    Inventors: Chien-Chang Tseng, Kuang-Hsiang Liu, Ya-Ting Yang
  • Patent number: 9136700
    Abstract: An electrostatic discharge protection circuit and a display apparatus are provided. The electrostatic discharge protection circuit adapted to the display apparatus having a display panel which has a signal line and a common voltage line. The electrostatic discharge protection circuit includes a first switching unit and a second switching unit. The first switching unit is electrically coupled to the signal line. The second switching unit is electronically coupled between the first switching unit and the common voltage line. When the display apparatus is shut down, the first switching unit and the second switching unit form a conductive path. When the display apparatus is turned on, the first switching unit receives a first control signal, and the second switching unit receives a second control signal, so that at least one of the first switching unit and the second switching unit is turned off at the same time.
    Type: Grant
    Filed: May 2, 2013
    Date of Patent: September 15, 2015
    Assignee: Au Optronics Corporation
    Inventors: Chien-Chang Tseng, Kuang-Hsiang Liu, Ya-Ting Yang
  • Patent number: 9129574
    Abstract: A gate driving circuit includes a shift register circuit and an auxiliary circuit which are disposed at different sides of a pixel array. The shift register circuit includes an (N?1)th shift register stage for generating an (N?1)th gate signal according to a first clock, an Nth shift register stage for generating an Nth gate signal according to a second clock, and an (N+1)th shift register stage for generating an (N+1)th gate signal according to a third clock. The auxiliary circuit includes a first transistor. The first transistor performs the signal voltage stabilization and level switching acceleration operations on the Nth gate signal according to the (N?1)th gate signal and the second clock.
    Type: Grant
    Filed: April 9, 2012
    Date of Patent: September 8, 2015
    Assignee: AU Optronics Corp.
    Inventors: Chien-Chang Tseng, Kuang-Hsiang Liu, Ya-Ting Yang
  • Patent number: 9030399
    Abstract: A gate driver for driving a TFT-LCD panel includes a number of gate-driver circuits arranged in groups and stages. Each gate-driver circuit has a main driver and an output section. The main driver is used to provide a charging signal to the output section which has two or more output circuits. Each of the output circuits is configured to provide a gate-line signal in response to the charging signal and a clock signal. The gate-driver circuit uses fewer switching elements, such as thin-film transistors, than the conventional circuit. When the gate driver is integrated in a TFT-LCD display panel and disposed within the periphery area around the display area, it is desirable to reduce or minimize the number of switching elements in the gate driver so that the periphery area can be reduced.
    Type: Grant
    Filed: February 23, 2012
    Date of Patent: May 12, 2015
    Assignee: AU Optronics Corporation
    Inventors: Chien-Chang Tseng, Kuang-Hsiang Liu, Sheng-Chao Liu, Che-Chia Chang, Ling-Ying Chien
  • Patent number: 8860651
    Abstract: A gate driver includes cascade-connected driving stages. Each of the driving stages includes a first shift register circuit and a second shift register circuit. The first shift register circuit is configured for outputting a present stage driving signal and a next stage driving signal. The second shift register circuit is electrically coupled to the first shift register circuit and configured for outputting a present stage gate signal, a first next stage gate signal, and a second next stage gate signal. Furthermore, a display panel is also provided herein.
    Type: Grant
    Filed: April 27, 2012
    Date of Patent: October 14, 2014
    Assignee: AU Optronics Corporation
    Inventors: Chien-Chang Tseng, Kuang-Hsiang Liu, Yu-Hsin Ting, Shih-Hsiang Chou, Ting-Jui Chang
  • Patent number: 8724406
    Abstract: A bidirectional shift register includes a first register circuit and a second register circuit. The first register circuit includes a first register stage and a first output buffer stage with n numbers of scanning signal output ends. The first register stage is electrically coupled to a third voltage source. The first output buffer stage is electrically coupled to a second voltage source and a first voltage source. The second register circuit has a similar circuit structure to the first register circuit; wherein the first register circuit and the second register circuit each use n+1 numbers clock signal lines, and the n is a positive integer.
    Type: Grant
    Filed: June 15, 2012
    Date of Patent: May 13, 2014
    Assignee: AU Optronics Corp.
    Inventors: Chien-Chang Tseng, Kuang-Hsiang Liu, Yu-Hsin Ting
  • Publication number: 20140071109
    Abstract: An electrostatic discharge protection circuit and a display apparatus are provided. The electrostatic discharge protection circuit adapted to the display apparatus having a display panel which has a signal line and a common voltage line. The electrostatic discharge protection circuit includes a first switching unit and a second switching unit. The first switching unit is electrically coupled to the signal line. The second switching unit is electronically coupled between the first switching unit and the common voltage line. When the display apparatus is shut down, the first switching unit and the second switching unit form a conductive path. When the display apparatus is turned on, the first switching unit receives a first control signal, and the second switching unit receives a second control signal, so that at least one of the first switching unit and the second switching unit is turned off at the same time.
    Type: Application
    Filed: May 2, 2013
    Publication date: March 13, 2014
    Applicant: Au Optronics Corporation
    Inventors: Chien-Chang Tseng, Kuang-Hsiang Liu, Ya-Ting Yang
  • Publication number: 20130222357
    Abstract: A gate driver for driving a TFT-LCD panel includes a number of gate-driver circuits arranged in groups and stages. Each gate-driver circuit has a main driver and an output section. The main driver is used to provide a charging signal to the output section which has two or more output circuits. Each of the output circuits is configured to provide a gate-line signal in response to the charging signal and a clock signal. The gate-driver circuit uses fewer switching elements, such as thin-film transistors, than the conventional circuit. When the gate driver is integrated in a TFT-LCD display panel and disposed within the periphery area around the display area, it is desirable to reduce or minimize the number of switching elements in the gate driver so that the periphery area can be reduced.
    Type: Application
    Filed: February 23, 2012
    Publication date: August 29, 2013
    Inventors: Chien-Chang TSENG, Kuang-Hsiang LIU, Sheng-Chao LIU, Che-Chia CHANG, Ling-Ying CHIEN
  • Publication number: 20130173870
    Abstract: A bidirectional shift register includes a first register circuit and a second register circuit. The first register circuit includes a first register stage and a first output buffer stage with n numbers of scanning signal output ends. The first register stage is electrically coupled to a third voltage source. The first output buffer stage is electrically coupled to a second voltage source and a first voltage source. The second register circuit has a similar circuit structure to the first register circuit; wherein the first register circuit and the second register circuit each use n+1 numbers clock signal lines, and the n is a positive integer.
    Type: Application
    Filed: June 15, 2012
    Publication date: July 4, 2013
    Applicant: AU OPTRONICS CORP.
    Inventors: Chien-Chang TSENG, Kuang-Hsiang Liu, Yu-Hsin Ting
  • Publication number: 20130135284
    Abstract: A gate driver includes cascade-connected driving stages. Each of the driving stages includes a first shift register circuit and a second shift register circuit. The first shift register circuit is configured for outputting a present stage driving signal and a next stage driving signal. The second shift register circuit is electrically coupled to the first shift register circuit and configured for outputting a present stage gate signal, a first next stage gate signal, and a second next stage gate signal. Furthermore, a display panel is also provided herein.
    Type: Application
    Filed: April 27, 2012
    Publication date: May 30, 2013
    Applicant: AU Optronics Corporation
    Inventors: Chien-Chang TSENG, Kuang-Hsiang Liu, Yu-Hsin Ting, Shih-Hsiang Chou, Ting-Jui Chang
  • Publication number: 20130127797
    Abstract: A gate driving circuit includes a shift register circuit and an auxiliary circuit which are disposed at different sides of a pixel array. The shift register circuit includes an (N?1)th shift register stage for generating an (N?1)th gate signal according to a first clock, an Nth shift register stage for generating an Nth gate signal according to a second clock, and an (N+1)th shift register stage for generating an (N+1)th gate signal according to a third clock. The auxiliary circuit includes a first transistor. The first transistor performs the signal voltage stabilization and level switching acceleration operations on the Nth gate signal according to the (N?1)th gate signal and the second clock.
    Type: Application
    Filed: April 9, 2012
    Publication date: May 23, 2013
    Inventors: Chien-Chang Tseng, Kuang-Hsiang Liu, Ya-Ting Yang
  • Patent number: 8259895
    Abstract: A bidirectional shift register includes first, second, third and fourth control signal bus lines for providing first, second, third and fourth control signals, Bi1, Bi2, Bi3 and Bi4, respectively, and a plurality of shift register stages electrically coupled in serial, each shift register stage having first and second input nodes, where the shift register stages are grouped into a first section and a second section, where the first and second input nodes of each shift register stage in the first section are electrically coupled to the first and second control signal bus lines for receiving the first and second control signals Bi1 and Bi2, respectively, and the first and second input nodes of each shift register stage in the second section are electrically coupled to the third and fourth control signal bus lines for receiving the third and fourth control signals Bi3 and Bi4, respectively.
    Type: Grant
    Filed: December 19, 2011
    Date of Patent: September 4, 2012
    Assignee: Au Optronics Corporation
    Inventors: Sheng-Chao Liu, Kuang-Hsiang Liu, Chien-Chang Tseng, Tsang-Hong Wang
  • Publication number: 20120087461
    Abstract: A bidirectional shift register includes first, second, third and fourth control signal bus lines for providing first, second, third and fourth control signals, Bi1, Bi2, Bi3 and Bi4, respectively, and a plurality of shift register stages electrically coupled in serial, each shift register stage having first and second input nodes, where the shift register stages are grouped into a first section and a second section, where the first and second input nodes of each shift register stage in the first section are electrically coupled to the first and second control signal bus lines for receiving the first and second control signals Bi1 and Bi2, respectively, and the first and second input nodes of each shift register stage in the second section are electrically coupled to the third and fourth control signal bus lines for receiving the third and fourth control signals Bi3 and Bi4, respectively.
    Type: Application
    Filed: December 19, 2011
    Publication date: April 12, 2012
    Applicant: AU OPTRONICS CORPORATION
    Inventors: Sheng-Chao Liu, Kuang-Hsiang Liu, Chien-Chang Tseng, Tsang-Hong Wang
  • Patent number: 8102962
    Abstract: A bidirectional shift register includes first, second, third and four control signal bus lines for providing first, second, third and fourth control signals, Bi1, Bi2, Bi3 and Bi4, respectively, and a plurality of shift register stages electrically coupled in serial, each shift register stage having a first input node and a second input node, where the plurality of shift register stages is grouped into a first section and a second section, wherein the first and second input nodes of each shift register stage in the first section are electrically coupled to the first and second control signal bus lines for receiving the first and second control signals Bi1 and Bi2, respectively, and the first and second input nodes of each shift register stage in the second section are electrically coupled to the third and fourth control signal bus lines for receiving the third and fourth control signals Bi3 and Bi4, respectively.
    Type: Grant
    Filed: January 11, 2010
    Date of Patent: January 24, 2012
    Assignee: AU Optronics Corporation
    Inventors: Sheng-Chao Liu, Kuang-Hsiang Liu, Chien-Chang Tseng, Tsang-Hong Wang
  • Publication number: 20110256415
    Abstract: A polypropylene anti-static membrane includes a PP (Polypropylene) board, which contains an anti-static agent to prevent from statics, and at least one surface of which is a cloudy surface. When the PP board is used as a base plate for cutting an optical material, such as a polarizer, tool marks that are left on a surface, while severing, can be restored, due to that the PP material is very firm and extremely flexible; therefore, fiber wires and powder will not be produced easily when the optical material is severed repeatedly. On the other hand, as the PP material is very firm and shock-proof, the optical material does not fracture easily and can be used longer. In addition, a probability that a surface of the optical product is damaged by pressing and scratching can be reduced.
    Type: Application
    Filed: January 27, 2009
    Publication date: October 20, 2011
    Inventor: Chien-Chang TSENG
  • Patent number: D1068970
    Type: Grant
    Filed: September 26, 2024
    Date of Patent: April 1, 2025
    Inventor: Chien Chang Tseng