Patents by Inventor Chien Chen Su

Chien Chen Su has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250110662
    Abstract: A computer vision processing system is provided. The system includes one or more target devices and a processing unit. The target devices are configured to run the executable code of an image processing pipeline. The processing unit is configured to receive a series of application programming interface (API) calls and create a raw graph accordingly, redraw the raw graph into a compilable graph by sequentially processing each node, and compile the compilable graph into the executable code of the image processing pipeline. The series of API calls includes at least one tiling API call to set at least one of the nodes and at least one of the data objects as tileable. Each tileable node corresponds to multiple parallel processing nodes in multiple branches in the compilable graph, and each tileable data object corresponds to multiple tile data objects in the branches in the compilable graph.
    Type: Application
    Filed: September 20, 2024
    Publication date: April 3, 2025
    Inventors: Po-Yuan JENG, Hung-Chun LIU, Yu-Chieh LIN, Chien-Han SU, Yung-Chih CHIU, Lei CHEN
  • Patent number: 11630500
    Abstract: Techniques for allocating power budget to a central processing unit (CPU) of a computing device are described. According to an example of the present subject matter, an unloaded component is detected. The unloaded component remains undetected upon completion of a boot process of the computing device. Thereafter, a power budget allocated to the unloaded component is determined. The power budget may be based on the thermal design power (TDP) of the computing device. Based on the power budget, a power configuration of the CPU is changed from a default power level to a high-performance power level, wherein the default power level corresponds to the TDP of the computing device and the high-performance power level is a power level above the default power level and upto a maximum power level of the CPU.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: April 18, 2023
    Assignee: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
    Inventors: Yen Tang Chang, Chao Wen Cheng, Chien Chen Su, Po Ying Chih
  • Publication number: 20220171446
    Abstract: Techniques for allocating power budget to a central processing unit (CPU) of a computing device are described. According to an example of the present subject matter, an unloaded component is detected. The unloaded component remains undetected upon completion of a boot process of the computing device. Thereafter, a power budget allocated to the unloaded component is determined. The power budget may be based on the thermal design power (TDP) of the computing device. Based on the power budget, a power configuration of the CPU is changed from a default power level to a high-performance power level, wherein the default power level corresponds to the TDP of the computing device and the high-performance power level is a power level above the default power level and upto a maximum power level of the CPU.
    Type: Application
    Filed: July 31, 2019
    Publication date: June 2, 2022
    Applicant: Hewlett-Packard Development Company, L.P.
    Inventors: Yen Tang Chang, Chao Wen Cheng, Chien Chen Su, Po Ying Chih
  • Publication number: 20220147127
    Abstract: Techniques for allocating power budget to a central processing unit (CPU) of a computing device are described. According to an example of the present subject matter, a CPU is operated at default power level corresponding to a thermal design power (TDP) of the computing device. Thereafter, an unused power of the computing device is determined at run-time. The unused power is a difference between an allocated power budget of the component and current power consumption of the component, wherein the allocated power budget is an amount of power allocated to the component based on the TDP of the computing device. Based on the unused power the CPU is operated at a high-performance power level. The high-performance power level is a power level above the default power and up to a maximum power level of the CPU.
    Type: Application
    Filed: July 31, 2019
    Publication date: May 12, 2022
    Applicant: Hewlett-Packard Development Company, L.P.
    Inventors: Po Ying Chih, Chao Wen Cheng, Yen Tang Chang, Wei Chieh Liao, Yu Fan Chen, Chien Chen Su