Abstract: A hot spot defect detecting method and a hot spot defect detecting system are provided. In the method, hot spots are extracted from a design of a semiconductor product to define a hot spot map comprising hot spot groups, wherein local patterns in a same context of the design yielding a same image content are defined as a same hot spot group. During runtime, defect images obtained by an inspection tool performing hot scans on a wafer manufactured with the design are acquired and the hot spot map is aligned to each defect image to locate the hot spot groups. The hot spot defects in each defect image are detected by dynamically mapping the hot spot groups located in each defect image to a plurality of threshold regions and respectively performing automatic thresholding on pixel values of the hot spots of each hot spot group in the corresponding threshold region.

Abstract: A mask for use in a semiconductor lithography process includes a substrate, a mask pattern disposed on the substrate, and a light absorbing border surrounding the mask pattern. The light absorbing border is inset from at least two edges of the substrate to define a peripheral region outside of the light absorbing border. In some designs, a first peripheral region extends from an outer perimeter of the light absorbing border to a first edge of the substrate, and a second peripheral region that extends from the outer perimeter of the light absorbing border to a second edge of the substrate, where the first edge of the substrate and the second edge of the substrate are on opposite sides of the mask pattern.

Abstract: A low pressure drop automotive liquid-cooling heat dissipation plate and an enclosed automotive liquid-cooling cooler having the same are provided. The low pressure drop automotive liquid-cooling heat dissipation plate includes a heat dissipation plate body and three fin sets. The heat dissipation plate body has a first heat dissipation surface and a second heat dissipation surface that are opposite to each other. The first heat dissipation surface is in contact with three traction inverter power component sets, and the second heat dissipation surface is in contact with a cooling fluid. Three heat dissipation regions that are spaced equidistantly apart from each other and that have a same size are defined on the second heat dissipation surface along a flow direction of the cooling fluid, and respectively correspond to three projection areas formed by projecting three traction inverter power component sets on the second heat dissipation surface.

Abstract: A low pressure drop automotive liquid-cooling heat dissipation plate and an enclosed automotive liquid-cooling cooler having the same are provided. The low pressure drop automotive liquid-cooling heat dissipation plate includes a heat dissipation plate body and three fin sets. The heat dissipation plate body has a first heat dissipation surface and a second heat dissipation surface that are opposite to each other. The first heat dissipation surface is in contact with three traction inverter power component sets, and the second heat dissipation surface is in contact with a cooling fluid. Three heat dissipation regions that are spaced equidistantly apart from each other and that have a same size are defined on the second heat dissipation surface along a flow direction of the cooling fluid, and respectively correspond to three projection areas formed by projecting three traction inverter power component sets on the second heat dissipation surface.

Abstract: A semiconductor package includes a first semiconductor die, an encapsulant, a high-modulus dielectric layer and a redistribution structure. The first semiconductor die includes a conductive post in a protective layer. The encapsulant encapsulates the first semiconductor die, wherein the encapsulant is made of a first material. The high-modulus dielectric layer extends on the encapsulant and the protective layer, wherein the high-modulus dielectric layer is made of a second material. The redistribution structure extends on the high-modulus dielectric layer, wherein the redistribution structure includes a redistribution dielectric layer, and the redistribution dielectric layer is made of a third material. The protective layer is made of a fourth material, and a ratio of a Young's modulus of the second material to a Young's modulus of the fourth material is at least 1.5.

Abstract: A method for manufacturing a circuit board structure with a waveguide is provided. The method includes: providing a first substrate unit, a second substrate unit, a third substrate unit, and two adhesive layers, the first substrate unit including a first dielectric layer and a first conductive layer, the first conductive layer including a first shielding area and two first artificial magnetic conductor areas disposed on two sides of the first shielding area; the second substrate unit including a second dielectric layer and a second conductive layer, the second conductive layer including a second shielding area; the third substrate unit defining a first slot, and the adhesive layer defining a second slot; stacking the first substrate unit, one of the adhesive layers, the third substrate unit, another one of the adhesive layers, and the second substrate unit in that order; pressing the intermediate body.

Abstract: A package structure and a method of forming the same are provided. The package structure includes a first die, a second die, a first encapsulant, and a buffer layer. The first die and the second die are disposed side by side. The first encapsulant encapsulates the first die and the second die. The second die includes a die stack encapsulated by a second encapsulant encapsulating a die stack. The buffer layer is disposed between the first encapsulant and the second encapsulant and covers at least a sidewall of the second die and disposed between the first encapsulant and the second encapsulant. The buffer layer has a Young's modulus less than a Young's modulus of the first encapsulant and a Young's modulus of the second encapsulant.

Abstract: A vehicle water-cooling heat sink plate having fin sets with different fin pitch distances is provided. The vehicle water-cooling heat sink plate includes a heat-dissipating plate body and three fin sets. The heat-dissipating plate body has a first heat-dissipating surface and a second heat-dissipating surface that are opposite to each other, the first heat-dissipating surface is used for contacting three traction inverter power component sets, and the second heat-dissipating surface is used for contacting a cooling fluid. The second heat-dissipating surface of the heat-dissipating plate body along a flow direction of the cooling fluid is divided into three heat-dissipating areas which are spaced apart from each other and have the same size, and the three heat-dissipating areas respectively correspond to three projection areas that are respectively generated by the three traction inverter power component sets.

Abstract: A vehicle water-cooling heat sink plate having fin sets with different surface areas is provided. The vehicle water-cooling heat sink plate includes a heat-dissipating plate body and three fin sets. The heat-dissipating plate body has a first heat-dissipating surface and a second heat-dissipating surface that are opposite to each other, the first heat-dissipating surface is used for contacting three traction inverter power component sets, and the second heat-dissipating surface is used for contacting a cooling fluid. The second heat-dissipating surface of the heat-dissipating plate body along a flow direction of the cooling fluid is divided into three heat-dissipating areas which are spaced apart from each other and have the same size, and the three heat-dissipating areas respectively correspond to three projection areas that are respectively generated by the three traction inverter power component sets.

Abstract: A semiconductor package includes a semiconductor die, a redistribution structure and connective terminals. The redistribution structure is disposed on the semiconductor die and includes a first metallization tier disposed in between a pair of dielectric layers. The first metallization tier includes routing conductive traces electrically connected to the semiconductor die and a shielding plate electrically insulated from the semiconductor die. The connective terminals include dummy connective terminals and active connective terminals. The dummy connective terminals are disposed on the redistribution structure and are electrically connected to the shielding plate. The active connective terminals are disposed on the redistribution structure and are electrically connected to the routing conductive traces. Vertical projections of the dummy connective terminals fall on the shielding plate.

Abstract: Embodiments provide a method of performing a carrier switch for a device wafer, attaching a second wafer and removing a first wafer. A buffer layer is deposited over the device wafer, buffer layer reducing the topography of the surface of the device wafer. After the carrier switch a film-on-wire layer is removed from the buffer layer and then the buffer layer is at least in part removed.

Abstract: A method includes forming a test pattern and a reference pattern in an absorption layer of a photomask structure. The test pattern has a first trench and a second trench, the reference pattern has a third trench and a fourth trench, the test pattern and the reference pattern have substantially the same dimension in a top view, and the second trench is deeper than the first trench, the third trench, and the fourth trench. The method further includes emitting a light beam to the test pattern to obtain a first interference pattern reflected from the test pattern, emitting the light beam to the reference pattern to obtain a second interference pattern reflected from the reference pattern; and comparing the first interference pattern with the second interference pattern to obtain a measured complex refractive index of the absorption layer.

Abstract: A static random access memory (SRAM) periphery circuit includes a first n-type transistor and a second n-type transistor that are disposed in a first well region of first conductivity type, the first well region occupies a first distance in a row direction equal to a bitcell-pitch of an SRAM array. The SRAM periphery circuit includes a first p-type transistor and a second p-type transistor that are disposed in a second well region of second conductivity type. The second well region occupies a second distance in the row direction equal to the bitcell-pitch of the SRAM array. The second well region is disposed adjacent to the first well region in the row direction.

Abstract: In a method of manufacturing an attenuated phase shift mask, a photo resist pattern is formed over a mask blank. The mask blank includes a transparent substrate, an etch stop layer on the transparent substrate, a phase shift material layer on the etch stop layer, a hard mask layer on the phase shift material layer and an intermediate layer on the hard mask layer. The intermediate layer is patterned by using the photo resist pattern as an etching mask, the hard mask layer is patterned by using the patterned intermediate layer as an etching mask, and the phase shift material layer is patterned by using the patterned hard mask layer as an etching mask. The intermediate layer includes at least one of a transition metal, a transition metal alloy, or a silicon containing material, and the hard mask layer is made of a different material than the intermediate layer.

Abstract: A device includes a semiconductor fin, and a gate stack on sidewalls and a top surface of the semiconductor fin. The gate stack includes a high-k dielectric layer, a work-function layer overlapping a bottom portion of the high-k dielectric layer, and a blocking layer overlapping a second bottom portion of the work-function layer. A low-resistance metal layer overlaps and contacts the work-function layer and the blocking layer. The low-resistance metal layer has a resistivity value lower than second resistivity values of both of the work-function layer and the blocking layer. A gate spacer contacts a sidewall of the gate stack.

Abstract: A high-frequency power module less vulnerable to parasitic phenomena includes first base board, power chip, and second base board. The first base board includes a first substrate, a first conductive wiring layer, and a second conductive wiring layer on each side of the first substrate. The power chip is disposed on the first conductive wiring layer. The second base board includes a second substrate covering the power chip and the first conductive wiring layer, and a third conductive wiring layer away from the first conductive wiring layer. First conductive structures penetrate the second substrate to connect the third conductive wiring layer with the power chip, greatly reducing the lengths of signal paths between components and so parasitic effects A second conductive structure penetrates the first and second substrates to connect the first, second, and third conductive wiring layers. A manufacturing method is also disclosed.

Abstract: A method for manufacturing a circuit board structure with a waveguide is provided. The method includes: providing a plate including a top wall and sidewalls disposed on the top wall, an opening being defined between ends of two adjacent sidewalls away from the top wall; forming a conductive layer on the plate to obtain a conductive plate; providing a circuit board, the circuit board comprising an outer circuit layer; mounting the conductive plate on the outer circuit layer, causing the outer circuit layer to be disposed on the opening. The two adjacent sidewalls, the top wall between the two adjacent sidewalls, and the circuit board between the two adjacent sidewalls cooperatively constitutes a tube body of the waveguide, and the conductive layer and the outer circuit layer on an inner surface of the tube body cooperatively constitute a shielding of the waveguide.

Abstract: A packaging structure and a circuit board having the packaging structure are provided. The packaging structure includes a power chip, a wire, a grid terminal, a first soldering layer, a second soldering layer, a first frame, a second frame, and a packaging body. The power chip has a grid electrode, a source electrode, and a drain electrode. The grid terminal is connected to the grid electrode through the wire. The first frame is connected to the source electrode through the first soldering layer. The second frame is connected to the drain electrode through the second soldering layer. The packaging body covers the power chip, the grid terminal, the first frame, the second frame, the wire, the first soldering layer and the second soldering layer.

Abstract: A method of manufacturing a circuit board having waveguides including forming a waveguiding structure by injection molding. The waveguiding structure includes a plurality of waveguides arranged at intervals and at least one connecting portion connecting two adjacent waveguides. Each waveguide includes a waveguiding substrate and at least one protrusion on the waveguiding substrate. The connecting portion is removed to obtain at least two waveguides. A metal layer is formed to wrap the whole outer surface of each waveguide. A plurality of receiving grooves is formed to penetrate a wiring board. Each waveguide wrapped by the metal layer is embedded in one of the receiving grooves. The waveguides and the wiring board are fixed. A portion of the metal layer on a surface of each protrusion facing away from the waveguiding substrate is removed. A circuit board is also provided.

Abstract: A method for manufacturing a circuit board structure with a waveguide is provided. The method includes: providing a plate including a top wall and sidewalls disposed on the top wall, an opening being defined between ends of two adjacent sidewalls away from the top wall; forming a conductive layer on the plate to obtain a conductive plate; providing a circuit board, the circuit board comprising an outer circuit layer; mounting the conductive plate on the outer circuit layer, causing the outer circuit layer to be disposed on the opening. The two adjacent sidewalls, the top wall between the two adjacent sidewalls, and the circuit board between the two adjacent sidewalls cooperatively constitutes a tube body of the waveguide, and the conductive layer and the outer circuit layer on an inner surface of the tube body cooperatively constitute a shielding of the waveguide.