Abstract: A chip packaging device includes a chip carrier, a chip and a packaging structure that includes a packaging plate and a connecting unit. The chip carrier includes a substrate and the chip is disposed thereon. The packaging plate and the substrate are respectively disposed at two opposite sides of the chip. The connecting unit has first and a second ends, which are respectively connected to the packaging plate and the chip. The first and second ends respectively have first and second cross-sectional areas perpendicular to an axis, and the second cross-sectional area is smaller than the first cross-sectional area.

Abstract: A fingerprint sensing device includes an insulating package, an image-sensing die, a light-emitting element, and a conductive component. The insulating package has a bottom surface and a top surface formed with first and second recesses. The image-sensing die is disposed in the first recess and has an outer surface exposed therefrom. The light-emitting element is disposed in the second recess and has an outer surface exposed from the second recess, and an electrode unit. The conductive component is formed in the insulating package, has top and bottom ends exposed from the top and bottom surfaces of the insulating package, and is electrically coupled to the image-sensing die and the electrode unit.

Abstract: A method for manufacturing a multilayer circuit board includes: forming a first patterned conductive layer on a ceramic substrate, the first patterned conductive layer having a first circuit pattern and a first submount pattern; forming a second patterned conductive layer on the first patterned conductive layer, the second patterned conductive layer having a second circuit pattern and a second submount pattern; forming an insulating layer on the ceramic substrate; and forming a third patterned conductive layer on the insulating layer. The third patterned conductive layer having a third circuit pattern and a third submount pattern. The first, second and third submount patterns are stacked one above another.

Abstract: A fingerprint sensing device includes an insulating package, an image-sensing die, a light-emitting element, and a conductive component. The insulating package has a bottom surface and a top surface formed with first and second recesses. The image-sensing die is disposed in the first recess and has an outer surface exposed therefrom. The light-emitting element is disposed in the second recess and has an outer surface exposed from the second recess, and an electrode unit. The conductive component is formed in the insulating package, has top and bottom ends exposed from the top and bottom surfaces of the insulating package, and is electrically coupled to the image-sensing die and the electrode unit.

Abstract: A fingerprint sensing device includes an insulating package, an image-sensing element, a light-emitting element, and a conductive component. The insulating package has a top surface that is formed with a first recess and a second recess, and a bottom surface that is opposite to the top surface. The conductive component is formed in the insulating package and has opposite top and bottom ends that are respectively exposed from the top and bottom surfaces of the insulating package. The image-sensing element is electrically connected to the conductive component by flip-chip techniques and has a sensing region that is exposed from the first recess. The light-emitting element is electrically coupled to the conductive component.

Abstract: A stress-reduced circuit board includes an insulating substrate, and first and second electrically conductive layers which are stacked one upon the other, and which respectively have peripheral marginal regions that are configured in a stepped arrangement. The first electrically conductive layer is configured to have an area dimension larger than that of the second electrically conductive layer and a thickness not greater than that of the second electrically conductive layer so as to minimize stress caused by a difference in coefficients of thermal expansion between the insulating substrate and the first and second electrically conductive layers.

Abstract: An interposer includes a substrate, an electrically-conductive structure, at least one dielectric layer, a redistribution structure and electrode pads. The substrate is made of a ceramic material and has first and second surfaces and via holes. The electrically-conductive structure includes conductive pads, substrate vias disposed in the via holes, and layered electrically-conductive parts. The dielectric layer is disposed on the second surface to cover the layered electrically-conductive parts. The redistribution structure penetrates the dielectric layer and is connected to the layered electrically-conductive parts. The electrode pads are disposed on a surface of the dielectric layer.

Abstract: A method for manufacturing a multilayer circuit board includes: forming a first patterned conductive layer on a ceramic substrate, the first patterned conductive layer having a first circuit pattern and a first submount pattern; forming a second patterned conductive layer on the first patterned conductive layer, the second patterned conductive layer having a second circuit pattern and a second submount pattern; forming an insulating layer on the ceramic substrate; and forming a third patterned conductive layer on the insulating layer. The third patterned conductive layer having a third circuit pattern and a third submount pattern. The first, second and third submount patterns are stacked one above another.

Abstract: An interposer includes a substrate, an electrically-conductive structure, at least one dielectric layer, a redistribution structure and electrode pads. The substrate is made of a ceramic material and has first and second surfaces and via holes. The electrically-conductive structure includes conductive pads, substrate vias disposed in the via holes, and layered electrically-conductive parts. The dielectric layer is disposed on the second surface to cover the layered electrically-conductive parts. The redistribution structure penetrates the dielectric layer and is connected to the layered electrically-conductive parts. The electrode pads are disposed on a surface of the dielectric layer.

Abstract: A stress-reduced circuit board includes an insulating substrate, and first and second electrically conductive layers which are stacked one upon the other, and which respectively have peripheral marginal regions that are configured in a stepped arrangement. The first electrically conductive layer is configured to have an area dimension larger than that of the second electrically conductive layer and a thickness not greater than that of the second electrically conductive layer so as to minimize stress caused by a difference in coefficients of thermal expansion between the insulating substrate and the first and second electrically conductive layers.

Abstract: A ceramic plate with reflective film and method of manufacturing the same are provided. The ceramic plate with reflective film at least comprises a ceramic substrate and a reflective film. The reflective film at least includes a glass layer and a metal film with metal crystals. Each of the metal crystals possesses a particular diameter for providing high infrared reflectivity with a particular wavelength.

Abstract: A low profile optoelectronic device package has a matalized transparent substrate, a chip and a dam ring. The matalized transparent substrate has a transparent board, a window area, and a metal pattern formed on a face of the transparent board and around the window area and having at least one outer contact pad and at least two contact pads. An active face of the chip is mounted to the at least two inner contact pads and aligned to the window area. A bottom face of the chip, that is opposite to the active face is further added a soldering layer. The dam ring is sealed a joint between the chip and the matalized transparent substrate so as to define an air cavity among the chip, the matalized transparent substrate and the dam ring. The matalized transparent substrate is used as a substrate and an optical cover of a conventional device package, so the optoelectronic device package provides low profile, small area outline, low fabricating cost and high lighting efficiency.

Abstract: This invention relates to a method for making a high-linearity and high-power CMOS structure and particularly to a field plate technology that is applied to a CMOS component, in which the field plate is formed on a dielectric layer of the CMOS, being arranged above a gate and a drain. An electric field is provided to significantly improve the RF linearity and output power of the CMOS component.

Abstract: This invention relates to a high-linearity and high-power CMOS structure and a method for the same and particularly to a field plate technology that is applied to a CMOS component, in which the field plate is formed on a dielectric layer of the CMOS, being arranged above a gate and a drain. An electric field is provided to significantly improve the RF linearity and output power of the CMOS component.