Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a plurality of semiconductor layers having a first group of semiconductor layers, a second group of semiconductor layers disposed over and aligned with the first group of semiconductor layers, and a third group of semiconductor layers disposed over and aligned with the second group of semiconductor layers. The structure further includes a first source/drain epitaxial feature in contact with a first number of semiconductor layers of the first group of semiconductor layers and a second source/drain epitaxial feature in contact with a second number of semiconductor layers of the third group of semiconductor layers. The first number of semiconductor layers of the first group of semiconductor layers is different from the second number of semiconductor layers of the third group of semiconductor layers.

Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a stack of semiconductor layers spaced apart from and aligned with each other, a first source/drain epitaxial feature in contact with a first one or more semiconductor layers of the stack of semiconductor layers, and a second source/drain epitaxial feature disposed over the first source/drain epitaxial feature. The second source/drain epitaxial feature is in contact with a second one or more semiconductor layers of the stack of semiconductor layers. The structure further includes a first dielectric material disposed between the first source/drain epitaxial feature and the second source/drain epitaxial feature and a first liner disposed between the first source/drain epitaxial feature and the second source/drain epitaxial feature. The first liner is in contact with the first source/drain epitaxial feature and the first dielectric material.

Abstract: The present disclosure describes a semiconductor structure with a dielectric liner. The semiconductor structure includes a substrate and a fin structure on the substrate. The fin structure includes a stacked fin structure, a fin bottom portion below the stacked fin structure, and an isolation layer between the stacked fin structure and the bottom fin portion. The semiconductor structure further includes a dielectric liner in contact with an end of the stacked fin structure and a spacer structure in contact with the dielectric liner.

Abstract: A method for forming a gate all around transistor includes forming a plurality of semiconductor nanosheets. The method includes forming a cladding inner spacer between a source region of the transistor and a gate region of the transistor. The method includes forming sheet inner spacers between the semiconductor nanosheets in a separate deposition process from the cladding inner spacer.

Abstract: An exemplary imaging module package includes a lens module and an imaging sensor module. The lens module includes a housing having a hollow top portion and a hollow bottom portion coaxially aligned with the hollow top portion. The imaging sensor module is received in the hollow bottom portion. The imaging sensor module includes an imaging sensor connected to the substrate and secured to the bottom portion, a substrate spaced from the bottom portion and defining at least one recess therein, and a plurality of passive components received in the at least one recess and wholly disposed below the imaging sensor.

Abstract: An exemplary camera module includes a substrate, a printed circuit board, an imaging sensor chip, and a lens module. The substrate defines a top surface and a recessed portion in the top surface. The printed circuit board defines a bottom surface soldered to the top surface of the substrate. The imaging sensor chip is received in the recessed portion of the substrate. The lens module is positioned above the imaging sensor chip, with an optical center thereof aligned with that of the imaging sensor chip.

Abstract: An exemplary imaging module package includes a housing, an imaging sensor module, and a lens module. The housing includes a first chamber and a second chamber coaxially aligned with the first chamber. The imaging sensor module is positioned within the first chamber and includes a substrate, an imaging sensor, a plurality of passive components and a plurality of soldering pads. The soldering pads connect the imaging sensor to the substrate. The passive components are mounted to the substrate and wholly disposed below the imaging sensor. The lens module is positioned within the second chamber of the housing.

Abstract: An exemplary imaging module package includes a lens module and an imaging sensor module. The lens module includes a housing having a hollow top portion and a hollow bottom portion coaxially aligned with the hollow top portion. The imaging sensor module is received in the hollow bottom portion. The imaging sensor module includes an imaging sensor connected to the substrate and secured to the bottom portion, a substrate spaced from the bottom portion and defining at least one recess therein, and a plurality of passive components received in the at least one recess and wholly disposed below the imaging sensor.