Patents by Inventor Chien-Chi Chen

Chien-Chi Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220367398
    Abstract: Package structures and methods for manufacturing the same are provided. The package structure includes a first bump structure formed over a first substrate. The first bump structure includes a first pillar layer formed over the first substrate and a first barrier layer formed over the first pillar layer. In addition, the first barrier layer has a first protruding portion laterally extending outside a first edge of the first pillar layer. The package structure further includes a second bump structure bonded to the first bump structure through a solder joint. In addition, the second bump structure includes a second pillar layer formed over a second substrate and a second barrier layer formed over the second pillar layer. The first protruding portion of the first barrier layer is spaced apart from the solder joint.
    Type: Application
    Filed: July 26, 2022
    Publication date: November 17, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Hung CHEN, Yu-Nu HSU, Chun-Chen LIU, Heng-Chi HUANG, Chien-Chen LI, Shih-Yen CHEN, Cheng-Nan HSIEH, Kuo-Chio LIU, Chen-Shien CHEN, Chin-Yu KU, Te-Hsun PANG, Yuan-Feng WU, Sen-Chi CHIANG
  • Publication number: 20220359191
    Abstract: A tool and methods of removing films from bevel regions of wafers are disclosed. The bevel film removal tool includes an inner motor nested within an outer motor and a bevel brush secured to the outer motor. The bevel brush is adjustable radially outward to allow the wafer to be inserted in the bevel brush and to be secured to the inner motor. The bevel brush is adjustable radially inward to engage one or more sections of the bevel brush and to bring the bevel brush in contact with a bevel region of the wafer. Once engaged, a solution may be dispensed at the engaged sections of the bevel brush and the inner motor and the outer motor may be rotated such that the bevel brush is rotated against the wafer such that the bevel films of the wafer are both chemically and mechanically removed.
    Type: Application
    Filed: July 25, 2022
    Publication date: November 10, 2022
    Inventors: Hui-Chi Huang, Jeng-Chi Lin, Pin-Chuan Su, Chien-Ming Wang, Kei-Wei Chen
  • Publication number: 20220356496
    Abstract: Disclosed herein is an isolated strain of Roseburia hominis HGM001, which is deposited at Deutsche Sammlung von Mikroorganismen and Zellkulturen GmbH under an accession number DSM 34119. A method for producing butyric acid using the isolated strain of Roseburia hominis HGM001, a fermented culture produced by the method, and a method for alleviating an inflammatory disorder using the fermented culture are also disclosed.
    Type: Application
    Filed: April 11, 2022
    Publication date: November 10, 2022
    Inventors: Chien-Hsun Huang, Li-Wen Hsu, Jong-Shian Liou, I-Ching Chen, Sung-Yuan Hsieh, Chien-Chi Chen
  • Publication number: 20220328440
    Abstract: Semiconductor device packages and method are provided. A semiconductor device package according to the present disclosure includes a substrate including a first region, a passive device disposed over the first region of the substrate, a contact pad disposed over the passive device, a passivation layer disposed over the contact pad, a recess through the passivation layer, and an under-bump metallization (UBM) layer. The recess exposes the contact pad and the UBM layer includes an upper portion disposed over the passivation layer and a lower portion disposed over a sidewall of the recess. A projection of the upper portion of the UBM layer along a direction perpendicular to the substrate falls within an area of the contact pad.
    Type: Application
    Filed: June 30, 2022
    Publication date: October 13, 2022
    Inventors: Chih-Fan Huang, Hui-Chi Chen, Kuo-Chin Chang, Chien-Huang Yeh, Hong-Seng Shue, Dian-Hau Chen, Yen-Ming Chen
  • Publication number: 20220328077
    Abstract: Header circuitry for a memory device includes multiple backside power rails that form distinct voltage sources for a plurality of switching devices in the header circuitry. The header circuitry includes at least one region of a first conductivity type. A first section in the first region includes one backside power rail (BPR) that forms a first voltage source that provides a first voltage. A second section in the same first region includes another BPR that forms a second voltage source that provides a second voltage that is different from the first voltage.
    Type: Application
    Filed: June 29, 2022
    Publication date: October 13, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Haruki MORI, Chien-Chi TIEN, Chia-En HUANG, Hidehiro FUJIWARA, Yen-Huei CHEN, Feng-Lun CHEN
  • Patent number: 11469203
    Abstract: A method for forming a package structure includes forming an under bump metallization (UBM) layer over a metal pad and forming a photoresist layer over the UBM layer. The method further includes patterning the photoresist layer to form an opening in the photoresist layer. The method also includes forming a first bump structure over the first portion of the UBM layer. The first bump structure includes a first barrier layer over a first pillar layer. The method includes placing a second bump structure over the first bump structure. The second bump structure includes a second barrier layer over a second pillar layer. The method further includes reflowing the first bump structure and the second bump structure to form a solder joint between a first inter intermetallic compound (IMC) and a second IMC.
    Type: Grant
    Filed: October 16, 2020
    Date of Patent: October 11, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Hung Chen, Yu-Nu Hsu, Chun-Chen Liu, Heng-Chi Huang, Chien-Chen Li, Shih-Yen Chen, Cheng-Nan Hsieh, Kuo-Chio Liu, Chen-Shien Chen, Chin-Yu Ku, Te-Hsun Pang, Yuan-Feng Wu, Sen-Chi Chiang
  • Patent number: 11453743
    Abstract: A thermoset epoxy resin, its preparing composition and making process are disclosed. In particular, the thermoset epoxy resin is glycidyl ether of diphenolic bis-carbamate and formed by curing a one component epoxy composition and has a general structure as shown in formula (1).
    Type: Grant
    Filed: June 5, 2020
    Date of Patent: September 27, 2022
    Assignee: CHANDA CHEMICAL CORP.
    Inventors: Chien-Hsin Wu, Ying-Chi Huang, Kuan-Ting Chen, Chia-Hsuan Lin, Sheng-Hong A. Dai, Ru-Jong Jeng
  • Patent number: 11435640
    Abstract: A cholesteric liquid crystal display includes a cholesteric liquid crystal device, a color filter element, a first quarter-wave plate, and a light recovery structure. The cholesteric liquid crystal device includes a cholesteric liquid crystal. The color filter element and the first quarter-wave plate overlap the cholesteric liquid crystal device. The first quarter-wave plate and the color filter element are located between the cholesteric liquid crystal and the light recovery structure.
    Type: Grant
    Filed: September 28, 2021
    Date of Patent: September 6, 2022
    Assignee: AU Optronics Corporation
    Inventors: Hao-Shiun Yang, Jian-Fu Chen, Chien-Chi Chen, Shang-Chiang Lin
  • Publication number: 20220278159
    Abstract: An image sensor device is provided. The image sensor device includes a semiconductor substrate having a front surface, a back surface opposite to the front surface, and a light-sensing region close to the front surface. The image sensor device includes an insulating layer covering the back surface and extending into the semiconductor substrate. The protection layer has a first refractive index, and the first refractive index is less than a second refractive index of the semiconductor substrate and greater than a third refractive index of the insulating layer, and the protection layer conformally and continuously covers the back surface and extends into the semiconductor substrate. The image sensor device includes a reflective structure surrounded by insulating layer in the semiconductor substrate.
    Type: Application
    Filed: May 18, 2022
    Publication date: September 1, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Chieh FANG, Ming-Chi WU, Ji-Heng JIANG, Chi-Yuan WEN, Chien-Nan TU, Yu-Lung YEH, Shih-Shiung CHEN, Kun-Yu LIN
  • Publication number: 20220248997
    Abstract: The present disclosure provides a method for detecting the focus of attention. The method includes: obtaining the face of a person in the first image, as well as the result of facial recognition; determining whether the distance between the person and the target is within an effective attention range; determining whether the face is frontal; determining whether the effective attention period is not shorter than a period threshold; detecting the focus of attention for the person to the target.
    Type: Application
    Filed: March 17, 2021
    Publication date: August 11, 2022
    Inventors: Kuan-Chung HOU, Bo-Ting WU, Chian-Ying LI, Ming-Hsuan TU, Chien-Hung LIN, Jian-Chi LIN, Fu-Heng WU, Kai-Lun CHANG, Tsung-Yao CHEN
  • Publication number: 20220241321
    Abstract: Pharmaceutical compositions comprising a CpG oligonucleotide, a buffer agent, and one or more salts having a total salt concentration of about 80-130 mM. A majority population of the CpG oligonucleotides in the composition is in dimeric form. Also provided herein are uses of the pharmaceutical compositions for modulating immune responses in subjects in need of the treatment, for example, cancer patient.
    Type: Application
    Filed: May 8, 2020
    Publication date: August 4, 2022
    Inventors: Yi-Chung CHANG, Shih-Chi YEH, Chih-Keng CHEN, Chien-Hao CHANG, Chu-Ying PENG
  • Publication number: 20220236608
    Abstract: Provided is a display apparatus including a first display panel, a second display panel, and at least one light-absorbing layer. The first display panel has a first splicing surface. The second display panel has a second splicing surface opposite to the first splicing surface. The at least one light-absorbing layer is disposed on at least one of the first splicing surface and the second splicing surface.
    Type: Application
    Filed: October 25, 2021
    Publication date: July 28, 2022
    Applicant: Au Optronics Corporation
    Inventors: Hao-Shiun Yang, Chien-Chi Chen, Shang-Chiang Lin
  • Publication number: 20220238572
    Abstract: A method includes etching a semiconductor substrate to form a trench, filling a dielectric layer into the trench, with a void being formed in the trench and between opposite portions of the dielectric layer, etching the dielectric layer to reveal the void, forming a diffusion barrier layer on the dielectric layer, and forming a high-reflectivity metal layer on the diffusion barrier layer. The high-reflectivity metal layer has a portion extending into the trench. A remaining portion of the void is enclosed by the high-reflectivity metal layer.
    Type: Application
    Filed: April 11, 2022
    Publication date: July 28, 2022
    Inventors: Ming-Chi Wu, Chun-Chieh Fang, Bo-Chang Su, Chien Nan Tu, Yu-Lung Yeh, Kun-Yu Lin, Shih-Shiung Chen
  • Patent number: 11398257
    Abstract: Header circuitry for a memory device includes multiple backside power rails that form distinct voltage sources for a plurality of switching devices in the header circuitry. The header circuitry includes at least one region of a first conductivity type. A first section in the first region includes one backside power rail (BPR) that forms a first voltage source that provides a first voltage. A second section in the same first region includes another BPR that forms a second voltage source that provides a second voltage that is different from the first voltage.
    Type: Grant
    Filed: October 30, 2020
    Date of Patent: July 26, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Haruki Mori, Chien-Chi Tien, Chia-En Huang, Hidehiro Fujiwara, Yen-Huei Chen, Feng-Lun Chen
  • Patent number: 11380639
    Abstract: Semiconductor device packages and method are provided. A semiconductor device package according to the present disclosure includes a substrate including a first region, a passive device disposed over the first region of the substrate, a contact pad disposed over the passive device, a passivation layer disposed over the contact pad, a recess through the passivation layer, and an under-bump metallization (UBM) layer. The recess exposes the contact pad and the UBM layer includes an upper portion disposed over the passivation layer and a lower portion disposed over a sidewall of the recess. A projection of the upper portion of the UBM layer along a direction perpendicular to the substrate falls within an area of the contact pad.
    Type: Grant
    Filed: December 7, 2020
    Date of Patent: July 5, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Fan Huang, Hui-Chi Chen, Kuo-Chin Chang, Chien-Huang Yeh, Hong-Seng Shue, Dian-Hau Chen, Yen-Ming Chen
  • Publication number: 20220209714
    Abstract: A crystal oscillator and a phase noise reduction method thereof are provided. The crystal oscillator may include a crystal oscillator core circuit, a first bias circuit and a phase noise reduction circuit, the first bias circuit is coupled to an output terminal of the crystal oscillator core circuit, and the phase noise reduction circuit is coupled to the output terminal of the crystal oscillator core circuit. In operations of the crystal oscillator, the crystal oscillator core circuit is configured to generate a sinusoidal wave. The first bias circuit is configured to provide a first voltage level to be a bias voltage of the sinusoidal wave. The phase noise reduction circuit is configured to reset the bias voltage of the sinusoidal wave in response to a voltage level of the sinusoidal wave exceeding a specific voltage range. For example, the specific voltage range is determined according to a second voltage level.
    Type: Application
    Filed: March 14, 2022
    Publication date: June 30, 2022
    Applicant: MEDIATEK INC.
    Inventors: Sen-You Liu, Chien-Wei Chen, Keng-Meng Chang, Yao-Chi Wang
  • Publication number: 20220209715
    Abstract: A crystal oscillator and a phase noise reduction method thereof are provided. The crystal oscillator includes a crystal oscillator core circuit, a bias circuit coupled to an output terminal of the crystal oscillator core circuit, a pulse wave buffer coupled to the output terminal of the crystal oscillator core circuit, and a phase noise reduction circuit coupled to the output terminal of the crystal oscillator core circuit. The crystal oscillator core circuit may generate a sinusoidal wave. The bias circuit may provide a bias voltage of the sinusoidal wave. The pulse wave buffer may generate a pulse wave according to the sinusoidal wave. The phase noise reduction circuit may provide an alternating current (AC) ground path for noise on the bias voltage according to a reset pulse, wherein a position of the reset pulse is set by a control voltage on a control terminal of the phase noise reduction circuit.
    Type: Application
    Filed: March 16, 2022
    Publication date: June 30, 2022
    Applicant: MEDIATEK INC.
    Inventors: Chien-Wei Chen, Yu-Li Hsueh, Keng-Meng Chang, Yao-Chi Wang
  • Patent number: 11314138
    Abstract: The present invention provides a display device including a display panel having a display surface, a polarizer disposed on the display surface, a first phase retardation layer disposed on one side of the polarizer opposite to the display surface, a polymerized cholesteric material layer disposed on one side of the first phase retardation layer opposite to the display surface, a second phase retardation layer disposed on one side of the polymerized cholesteric material layer opposite to the display surface, and a switchable polarizer disposed on one side of the second phase retardation layer opposite to the display surface. A first optical axis of the first phase retardation layer is orthogonal to a second optical axis of the second phase retardation layer. A first absorption axis of the polarizer is in the same direction as a second absorption axis of the switchable polarizer.
    Type: Grant
    Filed: January 27, 2021
    Date of Patent: April 26, 2022
    Assignee: AU OPTRONICS CORPORATION
    Inventors: Chien-Chi Chen, Wang-Shuo Kao, Hao-Shiun Yang, Shang-Chiang Lin
  • Publication number: 20210286205
    Abstract: The present invention provides a display device including a display panel having a display surface, a polarizer disposed on the display surface, a first phase retardation layer disposed on one side of the polarizer opposite to the display surface, a polymerized cholesteric material layer disposed on one side of the first phase retardation layer opposite to the display surface, a second phase retardation layer disposed on one side of the polymerized cholesteric material layer opposite to the display surface, and a switchable polarizer disposed on one side of the second phase retardation layer opposite to the display surface. A first optical axis of the first phase retardation layer is orthogonal to a second optical axis of the second phase retardation layer. A first absorption axis of the polarizer is in the same direction as a second absorption axis of the switchable polarizer.
    Type: Application
    Filed: January 27, 2021
    Publication date: September 16, 2021
    Inventors: Chien-Chi CHEN, Wang-Shuo KAO, Hao-Shiun YANG, Shang-Chiang LIN
  • Patent number: 10393924
    Abstract: A polarizer includes an adhesive, a first protective layer, a substrate layer, a second protective layer and a surface protective film. The surface protective film includes a plurality of first particles. Each of the first particles has a first particle size. The first particle size is greater than or equal to 10 ?m.
    Type: Grant
    Filed: August 30, 2017
    Date of Patent: August 27, 2019
    Assignee: AU OPTRONICS CORPORATION
    Inventors: Chien-Chi Chen, Yu-Han Chiang, Shang-Chiang Lin, Chen-Hsien Liao