Abstract: Systems, methods, and devices are described herein for integrated circuit (IC) layout validation. A plurality of IC patterns are collected which include a first set of patterns capable of being manufactured and a second set of patterns incapable of being manufactured. A machine learning model is trained using the plurality of IC patterns. The machine learning model generates a prediction model for validating IC layouts. The prediction model receives data including a set of test patterns comprising scanning electron microscope (SEM) images of IC patterns. Design violations associated with an IC layout are determined based on the SEM images and the plurality of IC patterns. A summary of the design violations is provided for further characterization of the IC layout.

Abstract: A system and a method for parameter optimization with adaptive search space and a user interface using the same are provided. The system includes a data acquisition unit, an adaptive adjustment unit and an optimization search unit. The data acquisition unit obtains a set of executed values of several operating parameters and a target parameter. The adaptive adjustment unit includes a parameter space transformer and a search range definer. The parameter space transformer performs a space transformation on a parameter space of the operating parameters according to the executed values. The search range definer defines a parameter search range in a transformed parameter space based on the sets of the executed values. The optimization search unit takes the parameter search range as a limiting condition and takes optimizing the target parameter as a target to search for a set of recommended values of the operating parameters.

Abstract: A media docking device includes an input circuit, an output circuit and a processing circuit. The input circuit is electrically connected to a media source device for receiving media data. The output circuit is electrically connected to a media play device. The processing circuit is electrically connected to the input circuit and the output circuit. The processing circuit determines if a verification procedure is passed. If the verification procedure is passed, the processing circuit transfers the media data to the media play device. If the verification procedure is not passed, the processing circuit limits a transmission of the media data, such that the media data will not be completely played by the media play device.

Abstract: A media docking device includes an input module, an output module and a processing module. The input module is electrically connected to a media source device for receiving media data. The output module is electrically connected to a media play device. The processing module determines if an instruction is received from the media source device or a remote device. If the instruction is not received, the processing module transfers the media data to the output module to transmit to the media play device. If the instruction is received, the processing module limits a transmission of the media data according to the instruction, such that the media data will not be completely played by the media play device.

Abstract: A novel additive for recycling thermoset materials, its related recyclable thermoset composition and its application are disclosed. Specifically, the composition of the additive comprises at least one copolymer that has at least one carbamate group, at least one carbonate group and/or at least one urea group, and a number-average molecular weight of the copolymer is between 100 and 50,000 Da.

Abstract: An acute kidney injury predicting system and a method thereof are proposed. A processor reads the data to be tested, the detection data, the machine learning algorithm and the risk probability comparison table from a main memory. The processor trains the detection data according to the machine learning algorithm to generate an acute kidney injury prediction model, and inputs the data to be tested into the acute kidney injury prediction model to generate an acute kidney injury characteristic risk probability and a data sequence table. The data sequence table lists the data to be tested in sequence according to a proportion of each of the data to be tested in the acute kidney injury characteristics. The processor selects one of the medical treatment data from the risk probability comparison table according to the acute kidney injury characteristic risk probability.

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, a stacked gate structure, and a wall structure. The stacked gate structure is on the substrate and extending along a first direction. The wall structure is on the substrate and laterally aside the stacked gate structure. The wall structure extends along the first direction and a second direction perpendicular to the first direction. The stacked gate structure is overlapped with the wall structure in the first direction and the second direction.

Abstract: Systems, methods, and devices are described herein for integrated circuit (IC) layout validation. A plurality of IC patterns are collected which include a first set of patterns capable of being manufactured and a second set of patterns incapable of being manufactured. A machine learning model is trained using the plurality of IC patterns. The machine learning model generates a prediction model for validating IC layouts. The prediction model receives data including a set of test patterns comprising scanning electron microscope (SEM) images of IC patterns. Design violations associated with an IC layout are determined based on the SEM images and the plurality of IC patterns. A summary of the design violations is provided for further characterization of the IC layout.

Abstract: A semiconductor device includes a substrate and a gate structure. The gate structure is disposed on the substrate, and the gate structure includes a titanium nitride barrier layer a titanium aluminide layer, and a middle layer. The titanium aluminide layer is disposed on the titanium nitride barrier layer, and the middle layer is disposed between the titanium aluminide layer and the titanium nitride barrier layer. The middle layer is directly connected with the titanium aluminide layer and the titanium nitride barrier layer, and the middle layer includes titanium and nitrogen. A concentration of nitrogen in the middle layer is gradually decreased in a vertical direction towards an interface between the middle layer and the titanium aluminide layer.

Abstract: Provided is a display apparatus including a first display panel, a second display panel, and at least one light-absorbing layer. The first display panel has a first splicing surface. The second display panel has a second splicing surface opposite to the first splicing surface. The at least one light-absorbing layer is disposed on at least one of the first splicing surface and the second splicing surface.

Abstract: Disclosed herein is an isolated strain of Roseburia hominis HGM001, which is deposited at Deutsche Sammlung von Mikroorganismen and Zellkulturen GmbH under an accession number DSM 34119. A method for producing butyric acid using the isolated strain of Roseburia hominis HGM001, a fermented culture produced by the method, and a method for alleviating an inflammatory disorder using the fermented culture are also disclosed.

Abstract: A cholesteric liquid crystal display includes a cholesteric liquid crystal device, a color filter element, a first quarter-wave plate, and a light recovery structure. The cholesteric liquid crystal device includes a cholesteric liquid crystal. The color filter element and the first quarter-wave plate overlap the cholesteric liquid crystal device. The first quarter-wave plate and the color filter element are located between the cholesteric liquid crystal and the light recovery structure.

Abstract: Provided is a display apparatus including a first display panel, a second display panel, and at least one light-absorbing layer. The first display panel has a first splicing surface. The second display panel has a second splicing surface opposite to the first splicing surface. The at least one light-absorbing layer is disposed on at least one of the first splicing surface and the second splicing surface.

Abstract: The present invention provides a display device including a display panel having a display surface, a polarizer disposed on the display surface, a first phase retardation layer disposed on one side of the polarizer opposite to the display surface, a polymerized cholesteric material layer disposed on one side of the first phase retardation layer opposite to the display surface, a second phase retardation layer disposed on one side of the polymerized cholesteric material layer opposite to the display surface, and a switchable polarizer disposed on one side of the second phase retardation layer opposite to the display surface. A first optical axis of the first phase retardation layer is orthogonal to a second optical axis of the second phase retardation layer. A first absorption axis of the polarizer is in the same direction as a second absorption axis of the switchable polarizer.

Abstract: The present invention provides a display device including a display panel having a display surface, a polarizer disposed on the display surface, a first phase retardation layer disposed on one side of the polarizer opposite to the display surface, a polymerized cholesteric material layer disposed on one side of the first phase retardation layer opposite to the display surface, a second phase retardation layer disposed on one side of the polymerized cholesteric material layer opposite to the display surface, and a switchable polarizer disposed on one side of the second phase retardation layer opposite to the display surface. A first optical axis of the first phase retardation layer is orthogonal to a second optical axis of the second phase retardation layer. A first absorption axis of the polarizer is in the same direction as a second absorption axis of the switchable polarizer.

Abstract: A polarizer includes an adhesive, a first protective layer, a substrate layer, a second protective layer and a surface protective film. The surface protective film includes a plurality of first particles. Each of the first particles has a first particle size. The first particle size is greater than or equal to 10 ?m.

Abstract: An apparatus for motion compensated noise reduction for input images is provided. The motion estimation and motion compensation circuit performs a motion estimation operation and a motion compensation operation on a current image and a previous image to obtain a first patch. The block matching operation circuit performs a block matching operation on the current image and the previous image to obtain a second patch. The motion detection circuit performs a motion detection operation on a target patch according to the first patch and the second patch to output a set of third patches. The current image includes the target patch. The noise reduction circuit performs a noise reduction operation on the set of third patches according to a threshold curve, so as to generate the target patch that the noise is reduced. A method for motion compensated noise reduction for input images is also provided.

Abstract: A polarizer includes an adhesive, a first protective layer, a substrate layer, a second protective layer and a surface protective film. The surface protective film includes a plurality of first particles. Each of the first particles has a first particle size. The first particle size is greater than or equal to 10 ?m.

Abstract: An apparatus for motion compensated noise reduction for input images is provided. The motion estimation and motion compensation circuit performs a motion estimation operation and a motion compensation operation on a current image and a previous image to obtain a first patch. The block matching operation circuit performs a block matching operation on the current image and the previous image to obtain a second patch. The motion detection circuit performs a motion detection operation on a target patch according to the first patch and the second patch to output a set of third patches. The current image includes the target patch. The noise reduction circuit performs a noise reduction operation on the set of third patches according to a threshold curve, so as to generate the target patch that the noise is reduced. A method for motion compensated noise reduction for input images is also provided.

Abstract: A testing system for a wafer having a plurality of flash memory dies is provided. The testing system includes a testing apparatus and a probe card coupled to the testing apparatus via a specific transmission line. The testing apparatus provides a testing requirement. The probe card includes a plurality of probes and a controller. The probes contact with at least one of the flash memory dies of the wafer. The controller writes a testing data to the flash memory die according to the testing requirement and reads the testing data from the flash memory die via the probes. The controller provides a testing result to the testing apparatus according to the read testing data.