Patents by Inventor Chien-Chi KUO

Chien-Chi KUO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Automated inspection tool
    Patent number: 11961770
    Abstract: Some embodiments of the present disclosure relate to a processing tool. The tool includes a housing enclosing a processing chamber, and an input/output port configured to pass a wafer through the housing into and out of the processing chamber. A back-side macro-inspection system is arranged within the processing chamber and is configured to image a back side of the wafer. A front-side macro-inspection system is arranged within the processing chamber and is configured to image a front side of the wafer according to a first image resolution. A front-side micro-inspection system is arranged within the processing chamber and is configured to image the front side of the wafer according to a second image resolution which is higher than the first image resolution.
    Type: Grant
    Filed: November 4, 2021
    Date of Patent: April 16, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Han Lin, Chien-Fa Lee, Hsu-Shui Liu, Jiun-Rong Pai, Sheng-Hsiang Chuang, Surendra Kumar Soni, Shou-Wen Kuo, Wu-An Weng, Gary Tsai, Chien-Ko Liao, Ya Hsun Hsueh, Becky Liao, Ethan Yu, Ming-Chi Tsai, Kuo-Yi Liu
  • Semiconductor device
    Patent number: 11948999
    Abstract: A device includes a first semiconductor fin, a second semiconductor fin, a source/drain epitaxial structure, a semiconductive cap, and a contact. The first semiconductor fin and the second semiconductor fin are over a substrate. The source/drain epitaxial structure is connected to the first semiconductor fin and the second semiconductor fin. The source/drain epitaxial structure includes a first protruding portion and a second protruding portion aligned with the first semiconductor fin and the second semiconductor fin, respectively. The semiconductive cap is on and in contact with the first protruding portion and the second protruding portion. A top surface of the semiconductive cap is lower than a top surface of the first protruding portion of the source/drain epitaxial structure. The contact is electrically connected to the source/drain epitaxial structure and covers the semiconductive cap.
    Type: Grant
    Filed: July 26, 2022
    Date of Patent: April 2, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yen-Ru Lee, Chii-Horng Li, Chien-I Kuo, Heng-Wen Ting, Jung-Chi Tai, Lilly Su, Yang-Tai Hsiao
  • Semiconductor device package and method of manufacturing the same
    Patent number: 11393776
    Abstract: A semiconductor device package includes a substrate, a first coil, a dielectric layer and a second coil. The first coil is disposed on the substrate. The first coil includes a first conductive segment and a second conductive segment. The dielectric layer covers the first conductive segment of the first coil and the second conductive segment of the first coil and defines a first recess between the first conductive segment of the first coil and the second conductive segment of the first coil. The second coil is disposed on the dielectric layer. The second coil has a first conductive segment disposed within the first recess.
    Type: Grant
    Filed: May 17, 2018
    Date of Patent: July 19, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Shun-Tsat Tu, Pei-Jen Lo, Yan-Si Lin, Chien-Chi Kuo
  • SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAME
    Publication number: 20190355676
    Abstract: A semiconductor device package includes a substrate, a first coil, a dielectric layer and a second coil. The first coil is disposed on the substrate. The first coil includes a first conductive segment and a second conductive segment. The dielectric layer covers the first conductive segment of the first coil and the second conductive segment of the first coil and defines a first recess between the first conductive segment of the first coil and the second conductive segment of the first coil. The second coil is disposed on the dielectric layer. The second coil has a first conductive segment disposed within the first recess.
    Type: Application
    Filed: May 17, 2018
    Publication date: November 21, 2019
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Shun-Tsat TU, Pei-Jen LO, Yan-Si LIN, Chien-Chi KUO