Patents by Inventor Chien-Chiang Chan

Chien-Chiang Chan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20110242726
    Abstract: An energy storage device is disclosed in the invention. The energy storage device includes a first electrode, a second electrode, a dielectric layer and a magnetic portion or a magnetic material. The dielectric layer is disposed between the first electrode and the second electrode. The dielectric layer cooperates with the first electrode and the second electrode for achieving the capacitance effect, such that a plurality of positive charges and a plurality of negative charges are accumulated on the first electrode and the second electrode. The magnetic portion or the magnetic material is used for establishing a magnetic field. The magnetic field passes through the first electrode, the dielectric layer and the second electrode.
    Type: Application
    Filed: March 28, 2011
    Publication date: October 6, 2011
    Inventor: Chien-Chiang CHAN
  • Publication number: 20100112438
    Abstract: An energy cell package includes an energy cell, a first metal substrate, a second metal substrate, at least one first jointing component, at least one second jointing component, and an insulating structure. The energy cell has at least one positive contact and at least one negative contact. The first metal substrate has an end functioning as an external positive contact. The second metal substrate has an end functioning as an external negative contact. The at least one first jointing component joints the at least one positive contact and the first metal substrate, and the at least one second jointing component joints the at least one negative contact and the second metal substrate. Except the external positive contact and external negative contact, the insulating structure coats the energy cell, first metal substrate, second metal substrate, at least one first jointing component, and at least one second jointing component.
    Type: Application
    Filed: December 5, 2008
    Publication date: May 6, 2010
    Inventor: Chien-Chiang CHAN
  • Publication number: 20100109609
    Abstract: A power supply module includes a circuit board and at least one energy cell. The energy cell has a positive contact and a negative contact. The energy cell is placed on the circuit board.
    Type: Application
    Filed: February 10, 2009
    Publication date: May 6, 2010
    Inventor: Chien-Chiang CHAN
  • Publication number: 20100015518
    Abstract: An applied structure of energy storage device is disclosed. The applied structure of energy storage device includes energy cells and at least one pair of positive and negative contact structures. Energy cells are arranged in a way facilitating the connecting of the energy cells in series or parallel. Each of the energy cells includes a flat type positive contact and a flat type negative contact. The flat type negative contact is arranged on the same or opposite sides of the flat type positive contact. The at least one pair of positive and negative contact structures are set for external connections.
    Type: Application
    Filed: September 18, 2008
    Publication date: January 21, 2010
    Inventor: Chien-Chiang Chan
  • Publication number: 20090085529
    Abstract: An electronics system module is provided. The electronics system module includes an electronics device and a power source. The power source includes a capacitor coupling to the electronics device and providing power thereto and an adjustable resistance connected in series between the capacitor and the electronics device. The resistance is adjusted by a control mechanism, so that the voltage supplied to the electronics device from the capacitor is constant.
    Type: Application
    Filed: October 1, 2007
    Publication date: April 2, 2009
    Inventors: Tom Allen Agan, James Chyi Lai, Chien-Chiang Chan
  • Publication number: 20080137399
    Abstract: A single chip has a substrate and at least one magnetoresistive memory layer. The substrate has an underlying memory and a control circuit. The magnetoresistive memory layer is placed on the substrate, and has a plurality of magnetoresistive random access memory cells controlled by the control circuit.
    Type: Application
    Filed: January 25, 2005
    Publication date: June 12, 2008
    Inventors: Chien-Chiang Chan, James Chyi Lai
  • Patent number: 7206221
    Abstract: An upside-down MRAM comprises a sense transistor and a plurality of sense lines. A first end of the sense transistor is electrically connected to a low voltage. The sense lines are electrically connected in parallel between a high voltage and a second end of the sense transistor. Each of the sense lines has a control logic and at least one memory bit, and the memory bit is connected in series between the high voltage and the control logic.
    Type: Grant
    Filed: September 9, 2005
    Date of Patent: April 17, 2007
    Assignee: Northern Lights Semiconductor Corp.
    Inventors: Tom Allen Agan, James Chyi Lai, Chien-Chiang Chan
  • Publication number: 20070058423
    Abstract: An upside-down MRAM comprises a sense transistor and a plurality of sense lines. A first end of the sense transistor is electrically connected to a low voltage. The sense lines are electrically connected in parallel between a high voltage and a second end of the sense transistor. Each of the sense lines has a control logic and at least one memory bit, and the memory bit is connected in series between the high voltage and the control logic.
    Type: Application
    Filed: September 9, 2005
    Publication date: March 15, 2007
    Inventors: Tom Agan, James Lai, Chien-Chiang Chan
  • Publication number: 20060268602
    Abstract: A memory comprises a plurality of memory units electrically connected. Each of the memory units comprises a pull-down transistor, a plurality of column lines and a selector. Each of the column lines has at least one bit. The selector is electrically connected between the pull-down transistor and the column lines. The selector is arranged to select one from the column lines to be accessed by the pull-down transistor. This results in a memory design that is faster, has more capability, is cheaper to build, quieter, and lower power.
    Type: Application
    Filed: May 19, 2006
    Publication date: November 30, 2006
    Inventors: Tom Agan, James Lai, Chien-Chiang Chan