Patents by Inventor Chien-Chiang LIN

Chien-Chiang LIN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12261203
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate including a base and a fin structure over the base. The fin structure includes a nanostructure. The semiconductor device structure includes a gate stack over the base and wrapped around the nanostructure. The gate stack has an upper portion and a sidewall portion, the upper portion is over the nanostructure, and the sidewall portion is over a first sidewall of the nanostructure. The semiconductor device structure includes a first inner spacer and a second inner spacer over opposite sides of the sidewall portion. A sum of a first width of the first inner spacer and a second width of the second inner spacer is greater than a third width of the sidewall portion as measured along a longitudinal axis of the fin structure.
    Type: Grant
    Filed: January 19, 2022
    Date of Patent: March 25, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chien-Chih Lin, Yun-Ju Pan, Szu-Chi Yang, Jhih-Yang Yan, Shih-Hao Lin, Chung-Shu Wu, Te-An Yu, Shih-Chiang Chen
  • Publication number: 20250081520
    Abstract: Embodiments with present disclosure provides a gate-all-around FET device including a patterned or lowered bottom dielectric layer. The bottom dielectric layer prevents the subsequently formed epitaxial source/drain region from volume loss and induces compressive strain in the channel region to prevent strain loss and channel resistance degradation.
    Type: Application
    Filed: January 5, 2024
    Publication date: March 6, 2025
    Inventors: Chien-Chia Cheng, Che-Yu Lin, Chih-Chiang Chang, Ming-Hua Yu, Chii-Horng Li
  • Publication number: 20250081529
    Abstract: Embodiments with present disclosure provides a gate-all-around FET device including extended bottom inner spacers. The extended bottom inner prevents the subsequently formed epitaxial source/drain region from volume loss and induces compressive strain in the channel region to prevent strain loss and channel resistance degradation.
    Type: Application
    Filed: March 1, 2024
    Publication date: March 6, 2025
    Inventors: Chien-Chia CHENG, Chih-Chiang CHANG, Ming-Hua YU, Chii-Horng LI, Chung-Ting KO, Sung-En LIN, Chih-Shan CHEN, De-Fang CHEN
  • Patent number: 12218075
    Abstract: A package structure includes an encapsulant, a patterned circuit structure, at least one electronic component and a shrinkage modifier. The patterned circuit structure is disposed on the encapsulant and includes a pad. The electronic component is disposed on the patterned circuit structure, and includes a bump electrically connected to the pad. The shrinkage modifier is encapsulated in the encapsulant and configured to reduce a relative displacement between the bump and the pad along a horizontal direction in an environment of temperature variation.
    Type: Grant
    Filed: December 30, 2021
    Date of Patent: February 4, 2025
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Cheng-Yuan Kung, Hsu-Chiang Shih, Hung-Yi Lin, Chien-Mei Huang
  • Publication number: 20250022957
    Abstract: The present disclosure provides a semiconductor device and a method of forming the same. A method according one embodiment of the present disclosure include forming a stack over a substrate, forming a fin-shape structure from patterning the stack and the substrate, recessing the fin-shape structure to form a source/drain trench, depositing a dielectric film in the source/drain trench with a top surface below a top surface of the substrate in the fin-shape structure, and forming an epitaxial feature over the dielectric film. A bottom surface of the epitaxial feature is below the top surface of the substrate in the fin-shape structure.
    Type: Application
    Filed: October 23, 2023
    Publication date: January 16, 2025
    Inventors: Che-Yu Lin, Chien-Chia Cheng, Chih-Chiang Chang, Chien-I Kuo, Ming-Hua Yu, Chii-Horng Li, Syun-Ming Jang, Wei-Jen Lo
  • Patent number: 10366932
    Abstract: A method for performing a wet chemical process over a semiconductor wafer is provided. The method includes moving the semiconductor wafer into a chemical solution. The method further includes detecting the concentration of at least one substance in the chemical solution at a plurality of preset time points. The method also includes removing the semiconductor wafer from the chemical solution, when the concentration of the substance is maintained at a fixed approximate value.
    Type: Grant
    Filed: June 8, 2017
    Date of Patent: July 30, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chien-Chiang Lin, Chung-Chen Yu, Shih-Chuan Lin, Zhi-Xioung Hu, Chih-Hung Hsueh
  • Publication number: 20180151456
    Abstract: A method for performing a wet chemical process over a semiconductor wafer is provided. The method includes moving the semiconductor wafer into a chemical solution. The method further includes detecting the concentration of at least one substance in the chemical solution at a plurality of preset time points. The method also includes removing the semiconductor wafer from the chemical solution, when the concentration of the substance is maintained at a fixed approximate value.
    Type: Application
    Filed: June 8, 2017
    Publication date: May 31, 2018
    Inventors: Chien-Chiang LIN, Chung-Chen YU, Shih-Chuan LIN, Zhi-Xioung HU, Chih-Hung HSUEH