Abstract: Examples of fabricating an integrated circuit device are disclosed herein. In an embodiment, an integrated circuit workpiece is received that includes a conductive interconnect feature. A first Inter-Level Dielectric (ILD) layer is formed on the conductive interconnect feature, and a second ILD layer is formed on the first ILD layer. A hard mask is formed on the second ILD layer. A via recess is etched extending through the first ILD layer, the second ILD layer and the hard mask to expose the conductive interconnect feature. The etching includes providing a passivation agent that reacts with a material of the hard mask to reduce etchant sensitivity.

Abstract: An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a low-k (LK) dielectric layer over a substrate; a first conductive feature in the LK dielectric layer, wherein the first conductive feature has a first sidewall, a second sidewall facing the first sidewall, and a first bottom surface contacting the LK dielectric layer; a first dielectric feature along an upper portion of the first sidewall, wherein a length of the first dielectric feature is at least 10 percent less than a length of the first sidewall; and a second dielectric feature along an upper portion of the second sidewall. The interconnect structure may also include a second conductive feature adjacent to the first conductive feature in the LK dielectric layer.

Abstract: An embodiment includes a method. The method includes: forming a first conductive line over a substrate; depositing a first dielectric layer over the first conductive line; depositing a second dielectric layer over the first dielectric layer, the second dielectric layer including a different dielectric material than the first dielectric layer; patterning a via opening in the first dielectric layer and the second dielectric layer, where the first dielectric layer is patterned using first etching process parameters, and the second dielectric layer is patterned using the first etching process parameters; patterning a trench opening in the second dielectric layer; depositing a diffusion barrier layer over a bottom and along sidewalls of the via opening, and over a bottom and along sidewalls of the trench opening; and filling the via opening and the trench opening with a conductive material.

Abstract: Semiconductor devices and methods of forming the same are disclosed. A dielectric layer is formed over an underlying layer. A first mask layer and a second mask layer are formed on the dielectric layer such that the first mask layer is interposed between the second mask layer and the dielectric layer. An opening is formed in the first mask layer, the second mask layer and the dielectric layer. Subsequently, the second mask layer is removed. The opening is extended and corners of the first mask layer are rounded. A conductive feature is formed in the extended opening.

Abstract: An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a low-k (LK) dielectric layer over a substrate; a first conductive feature in the LK dielectric layer, wherein the first conductive feature has a first sidewall, a second sidewall facing the first sidewall, and a first bottom surface contacting the LK dielectric layer; a first dielectric feature along an upper portion of the first sidewall, wherein a length of the first dielectric feature is at least 10 percent less than a length of the first sidewall; and a second dielectric feature along an upper portion of the second sidewall. The interconnect structure may also include a second conductive feature adjacent to the first conductive feature in the LK dielectric layer.

Abstract: A method of forming an interconnect structure is provided. The method includes forming a first dielectric layer, and forming an opening in the first dielectric layer. The method also includes applying a gas to the first dielectric layer adjacent to the opening, where after applying the gas to the first dielectric layer adjacent to the opening, a bottom surface of the opening has been planarized. The method also includes etching the first dielectric layer through the opening to expose a first contact underlying the first dielectric layer, and forming a conductive line in the opening.

Abstract: A method of forming an interconnect structure is provided. The method includes forming a first dielectric layer, and forming an opening in the first dielectric layer. The method also includes applying a gas to the first dielectric layer adjacent to the opening, where after applying the gas to the first dielectric layer adjacent to the opening, a bottom surface of the opening has been planarized. The method also includes etching the first dielectric layer through the opening to expose a first contact underlying the first dielectric layer, and forming a conductive line in the opening.

Abstract: An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a low-k (LK) dielectric layer over a substrate; a first conductive feature in the LK dielectric layer, wherein the first conductive feature has a first sidewall, a second sidewall facing the first sidewall, and a first bottom surface contacting the LK dielectric layer; a first dielectric feature along an upper portion of the first sidewall, wherein a length of the first dielectric feature is at least 10 percent less than a length of the first sidewall; and a second dielectric feature along an upper portion of the second sidewall. The interconnect structure may also include a second conductive feature adjacent to the first conductive feature in the LK dielectric layer.

Abstract: A method embodiment includes forming a hard mask over a dielectric layer, patterning the hard mask to form an opening, forming a passivation layer on sidewalls of the opening, and forming a trench in the dielectric layer by extending the opening into the dielectric layer using an etching process. The sidewalls of the opening are etched to form a rounded profile in the hard mask and a substantially perpendicular profile in the dielectric layer.

Abstract: Semiconductor devices and methods of forming the same are disclosed. A dielectric layer is formed over an underlying layer. A first mask layer and a second mask layer are formed on the dielectric layer such that the first mask layer is interposed between the second mask layer and the dielectric layer. An opening is formed in the first mask layer, the second mask layer and the dielectric layer. Subsequently, the second mask layer is removed. The opening is extended and corners of the first mask layer are rounded. A conductive feature is formed in the extended opening.

Abstract: An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a low-k (LK) dielectric layer over a substrate; a first conductive feature in the LK dielectric layer, wherein the first conductive feature has a first sidewall, a second sidewall facing the first sidewall, and a first bottom surface contacting the LK dielectric layer; a first dielectric feature along an upper portion of the first sidewall, wherein a length of the first dielectric feature is at least 10 percent less than a length of the first sidewall; and a second dielectric feature along an upper portion of the second sidewall. The interconnect structure may also include a second conductive feature adjacent to the first conductive feature in the LK dielectric layer.

Abstract: A method embodiment includes forming a hard mask over a dielectric layer, patterning the hard mask to form an opening, forming a passivation layer on sidewalls of the opening, and forming a trench in the dielectric layer by extending the opening into the dielectric layer using an etching process. The sidewalls of the opening are etched to form a rounded profile in the hard mask and a substantially perpendicular profile in the dielectric layer.

Abstract: An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a low-k (LK) dielectric layer over a substrate; a first conductive feature in the LK dielectric layer, wherein the first conductive feature has a first sidewall, a second sidewall facing the first sidewall, and a first bottom surface contacting the LK dielectric layer; a first dielectric feature along an upper portion of the first sidewall, wherein a length of the first dielectric feature is at least 10 percent less than a length of the first sidewall; and a second dielectric feature along an upper portion of the second sidewall. The interconnect structure may also include a second conductive feature adjacent to the first conductive feature in the LK dielectric layer.

Abstract: An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a low-k (LK) dielectric layer over a substrate; a first conductive feature in the LK dielectric layer, wherein the first conductive feature has a first sidewall, a second sidewall facing the first sidewall, and a first bottom surface contacting the LK dielectric layer; a first dielectric feature along an upper portion of the first sidewall, wherein a length of the first dielectric feature is at least 10 percent less than a length of the first sidewall; and a second dielectric feature along an upper portion of the second sidewall. The interconnect structure may also include a second conductive feature adjacent to the first conductive feature in the LK dielectric layer.

Abstract: A method embodiment includes forming a hard mask over a dielectric layer, patterning the hard mask to form an opening, forming a passivation layer on sidewalls of the opening, and forming a trench in the dielectric layer by extending the opening into the dielectric layer using an etching process. The sidewalls of the opening are etched to form a rounded profile in the hard mask and a substantially perpendicular profile in the dielectric layer.

Abstract: A method embodiment includes forming a hard mask over a dielectric layer, patterning the hard mask to form an opening, forming a passivation layer on sidewalls of the opening, and forming a trench in the dielectric layer by extending the opening into the dielectric layer using an etching process. The sidewalls of the opening are etched to form a rounded profile in the hard mask and a substantially perpendicular profile in the dielectric layer.

Abstract: A digital manipulator for an inverter and an image display method for the digital manipulator are disclosed. The digital manipulator is connected to and an external computer. The images used by the digital manipulator are edited by editing software in an external computer and are downloaded to LCM of the digital manipulator to display. The digital manipulator has a plurality of function buttons. Corresponding functions of the function buttons are assigned via editing software by a user. As a result, the digital manipulator is more flexible to use, and users are allowed to configure a digital manipulator based on own individual requests and operating habits.

Abstract: A digital manipulator for an inverter and an image display method for the digital manipulator are disclosed. The digital manipulator is connected to and an external computer. The images used by the digital manipulator are edited by editing software in an external computer and are downloaded to LCM of the digital manipulator to display. The digital manipulator has a plurality of function buttons. Corresponding functions of the function buttons are assigned via editing software by a user. As a result, the digital manipulator is more flexible to use, and users are allowed to configure a digital manipulator based on own individual requests and operating habits.

Abstract: A method for promoting proliferation and/or migration of skin cells includes providing a composition containing a compound of formula (I) below; and administrating to the skin cells the composition.

Abstract: A composition for promoting proliferation and/or migration of skin cells includes a compound of formula (I): or a pharmaceutically acceptable salt or ester thereof.