Patents by Inventor Chien-Chih Chou
Chien-Chih Chou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11133226Abstract: Various embodiments of the present disclosure are directed towards a method for forming a fully silicided (FUSI) gated device, the method including: forming a masking layer onto a gate structure over a substrate, the gate structure comprising a polysilicon layer. Forming a first source region and a first drain region on opposing sides of the gate structure within the substrate, the gate structure is formed before the first source and drain regions. Performing a first removal process to remove a portion of the masking layer and expose an upper surface of the polysilicon layer. The first source and drain regions are formed before the first removal process. Forming a conductive layer directly contacting the upper surface of the polysilicon layer. The conductive layer is formed after the first removal process. Converting the conductive layer and polysilicon layer into a FUSI layer. The FUSI layer is thin and uniform in thickness.Type: GrantFiled: October 24, 2018Date of Patent: September 28, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yi-Huan Chen, Chien-Chih Chou, Ta-Wei Lin, Hsiao-Chin Tuan, Alexander Kalnitsky, Kong-Beng Thei, Chia-Hong Wu
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Publication number: 20210273069Abstract: A transistor device with a recessed gate structure is provided. In some embodiments, the transistor device comprises a semiconductor substrate comprising a device region surrounded by an isolation structure and a pair of source/drain regions disposed in the device region and laterally spaced apart one from another in a first direction. A gate structure overlies the device region and the isolation structure and arranged between the pair of source/drain regions. The gate structure comprises a pair of recess regions disposed on opposite sides of the device region in a second direction perpendicular to the first direction. A channel region is disposed in the device region underneath the gate structure. The channel region has a channel width extending in the second direction from one of the recess regions to the other one of the recess regions.Type: ApplicationFiled: July 15, 2020Publication date: September 2, 2021Inventors: Chen-Liang Chu, Chien-Chih Chou, Chih-Chang Cheng, Yi-Huan Chen, Kong-Beng Thei, Ming-Ta Lei, Ruey-Hsin Liu, Ta-Yuan Kung
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Publication number: 20210265344Abstract: The present disclosure relates to an integrated circuit (IC) that includes a boundary region defined between a low voltage region and a high voltage region, and a method of formation. In some embodiments, the integrated circuit comprises an isolation structure disposed in the boundary region of the substrate. A first polysilicon component is disposed over the substrate alongside the isolation structure. A boundary dielectric layer is disposed on the isolation structure. A second polysilicon component is disposed on the sacrifice dielectric layer.Type: ApplicationFiled: February 21, 2020Publication date: August 26, 2021Inventors: Yi-Huan Chen, Chien-Chih Chou, Alexander Kalnitsky, Kong-Beng Thei, Ming Chyi Liu, Shi-Chung Hsiao, Jhih-Bin Chen
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Publication number: 20210193813Abstract: In some embodiments, an integrated circuit is provided. The integrated circuit may include an inner ring-shaped isolation structure that is disposed in a semiconductor substrate. Further, the inner-ring shaped isolation structure may demarcate a device region. An inner ring-shaped well is disposed in the semiconductor substrate and surrounds the inner ring-shaped isolation structure. A plurality of dummy gates are arranged over the inner ring-shaped well. Moreover, the plurality of dummy gates are arranged within an interlayer dielectric layer.Type: ApplicationFiled: March 4, 2021Publication date: June 24, 2021Inventors: Yi-Huan Chen, Chien-Chih Chou, Ta-Wei Lin, Fu-Jier Fan, Kong-Beng Thei, Yi-Sheng Chen, Szu-Hsien Liu
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Patent number: 11011619Abstract: In some embodiments, a semiconductor device is provided. The semiconductor device includes a pair of source/drain regions disposed in a semiconductor substrate, where the source/drain regions are laterally spaced. A gate electrode is disposed over the semiconductor substrate between the source/drain regions. Sidewall spacers are disposed over the semiconductor substrate on opposite sides of the gate electrode. A silicide blocking structure is disposed over the sidewalls spacers, where respective sides of the source/drain regions facing the gate electrode are spaced apart from outer sides of the sidewall spacers and are substantially aligned with outer sidewalls of the silicide blocking structure.Type: GrantFiled: September 6, 2019Date of Patent: May 18, 2021Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Kong-Beng Thei, Chien-Chih Chou, Hsiao-Chin Tuan, Yi-Huan Chen, Alexander Kalnitsky
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Patent number: 10991693Abstract: The present disclosure relates to an integrated circuit (IC) that includes a boundary region defined between a low voltage region, and a method of formation. In some embodiments, the integrated circuit comprises a first gate boundary dielectric layer disposed over a substrate in the low voltage region. A second gate boundary dielectric layer is disposed over the substrate in the high voltage region having a thickness greater than that of the first boundary dielectric layer. The first boundary dielectric layer meets the second boundary dielectric layer at the boundary region. A first polysilicon component is disposed within the boundary region over the first boundary dielectric layer and the second gate boundary layer. A second polysilicon component is disposed within the boundary region over the first polysilicon component. A hard mask component is disposed over the first polysilicon component and laterally neighbored to the second polysilicon component.Type: GrantFiled: January 2, 2020Date of Patent: April 27, 2021Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yi-Huan Chen, Chien-Chih Chou, Kong-Beng Thei
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Patent number: 10950708Abstract: In some embodiments, an integrated circuit is provided. The integrated circuit may include an inner ring-shaped isolation structure that is disposed in a semiconductor substrate. Further, the inner-ring shaped isolation structure may demarcate a device region. An inner ring-shaped well is disposed in the semiconductor substrate and surrounds the inner ring-shaped isolation structure. A plurality of dummy gates are arranged over the inner ring-shaped well. Moreover, the plurality of dummy gates are arranged within an interlayer dielectric layer.Type: GrantFiled: November 14, 2019Date of Patent: March 16, 2021Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yi-Huan Chen, Chien-Chih Chou, Ta-Wei Lin, Fu-Jier Fan, Kong-Beng Thei, Yi-Sheng Chen, Szu-Hsien Liu
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Patent number: 10930776Abstract: A semiconductor device is provided. The semiconductor device comprises a substrate, a gate, a first doped region and a second doped region. The gate is over the substrate. The first doped region and the second doped region are in the substrate. The first doped region and the second doped region are of a same conductivity type and separated by the gate. The length of the first doped region is greater than a length of the second doped region in a direction substantially perpendicular to a channel length defined between the first doped region and the second doped region.Type: GrantFiled: May 8, 2020Date of Patent: February 23, 2021Assignee: Taiwan Semiconductor Manufacturing Company Ltd.Inventors: Ker-Hsiao Huo, Kong-Beng Thei, Chien-Chih Chou, Yi-Min Chen, Chen-Liang Chu
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Publication number: 20200402978Abstract: The present disclosure relates to an integrated circuit (IC) and a method of formation. In some embodiments, a low voltage region and a high voltage region are integrated in a substrate. A low voltage transistor device is disposed in the low voltage region and comprises a low voltage gate electrode and a low voltage gate dielectric separating the low voltage gate electrode from the substrate. A first interlayer dielectric layer is disposed over the substrate surrounding the low voltage gate electrode and the low voltage gate dielectric. A high voltage transistor device is disposed in the high voltage region and comprises a high voltage gate electrode disposed on the first interlayer dielectric layer.Type: ApplicationFiled: September 2, 2020Publication date: December 24, 2020Inventors: Kong-Beng Thei, Chien-Chih Chou, Fu-Jier Fan, Hsiao-Chin Tuan, Yi-Huan Chen, Alexander Kalnitsky, Yi-Sheng Chen
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Patent number: 10868106Abstract: A method of manufacturing a semiconductor device and the semiconductor device are provided in which a plurality of layers with cobalt-zirconium-tantalum are formed over a semiconductor substrate, the plurality of layers are patterned, and multiple dielectric layers and conductive materials are deposited over the CZT material. Another layer of CZT material encapsulates the conductive material.Type: GrantFiled: May 13, 2019Date of Patent: December 15, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wei-Li Huang, Chi-Cheng Chen, Hon-Lin Huang, Chien-Chih Chou, Chin-Yu Ku, Chen-Shien Chen
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Publication number: 20200381420Abstract: Some embodiments relate to an integrated circuit (IC) that includes a semiconductor substrate. A shallow trench isolation region downwardly extends into the frontside of the semiconductor substrate and is filled with dielectric material. A first capacitor plate and a second capacitor plate are disposed in the shallow trench isolation region. The first capacitor plate and the second capacitor plate have first and second sidewall structures, respectively, that are substantially parallel to one another and that are separated from one another by the dielectric material of the shallow trench isolation region.Type: ApplicationFiled: September 23, 2019Publication date: December 3, 2020Inventors: Yi-Huan Chen, Chien-Chih Chou, Alexander Kalnitsky, Kong-Beng Thei
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Patent number: 10804093Abstract: In some embodiments, a bipolar junction transistor (BJT) is provided. The BJT may include a collector region that is disposed within a semiconductor substrate. A base region that is disposed within the semiconductor substrate and arranged within the collector region. An emitter region that is disposed within the semiconductor substrate and arranged within the base region. A pre-metal dielectric layer that is disposed over an upper surface of the semiconductor substrate and that separates the upper surface of the semiconductor substrate from a lowermost metal interconnect layer. A first plurality of dishing prevention columns that are arranged over the emitter region and within the pre-metal dielectric layer, where the plurality of dishing prevention columns each include a dummy gate that is conductive and electrically floating.Type: GrantFiled: September 30, 2019Date of Patent: October 13, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yi-Huan Chen, Chien-Chih Chou, Kong-Beng Thei, Meng-Han Lin
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Patent number: 10804220Abstract: In some embodiments, a bipolar junction transistor (BJT) is provided. The BJT may include a collector region that is disposed within a semiconductor substrate. A base region that is disposed within the semiconductor substrate and arranged within the collector region. An emitter region that is disposed within the semiconductor substrate and arranged within the base region. A pre-metal dielectric layer that is disposed over an upper surface of the semiconductor substrate and that separates the upper surface of the semiconductor substrate from a lowermost metal interconnect layer. A first plurality of dishing prevention columns that are arranged over the emitter region and within the pre-metal dielectric layer, where the plurality of dishing prevention columns each include a dummy gate that is conductive and electrically floating.Type: GrantFiled: September 30, 2019Date of Patent: October 13, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yi-Huan Chen, Chien-Chih Chou, Kong-Beng Thei, Meng-Han Lin
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Patent number: 10790387Abstract: A semiconductor device is provided. The semiconductor device comprises a substrate, a gate, a first doped region and a second doped region. The gate is over the substrate. The first doped region and the second doped region are in the substrate. The first doped region and the second doped region are of a same conductivity type and separated by the gate. The length of the first doped region is greater than a length of the second doped region in a direction substantially perpendicular to a channel length defined between the first doped region and the second doped region.Type: GrantFiled: March 5, 2018Date of Patent: September 29, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Ker-Hsiao Huo, Kong-Beng Thei, Chien-Chih Chou, Yi-Min Chen, Chen-Liang Chu
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Patent number: 10790279Abstract: The present disclosure relates to an integrated circuit (IC) and a method of formation. In some embodiments, a low voltage transistor device is disposed in a low voltage region defined on a substrate. The low voltage transistor device comprises a low voltage gate electrode and a first gate dielectric separating the low voltage gate electrode from the substrate. A high voltage transistor device is disposed in a high voltage region defined on the substrate. The high voltage transistor device comprises a high voltage gate electrode and a high voltage gate dielectric separating the high voltage gate electrode from the substrate. A first interlayer dielectric layer is disposed over the substrate surrounding the low voltage transistor device and the high voltage transistor device. The high voltage gate electrode is disposed on the first interlayer dielectric layer and separated from the substrate by the first interlayer dielectric layer.Type: GrantFiled: October 18, 2019Date of Patent: September 29, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kong-Beng Thei, Chien-Chih Chou, Fu-Jier Fan, Hsiao-Chin Tuan, Yi-Huan Chen, Alexander Kalnitsky, Yi-Sheng Chen
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Publication number: 20200266295Abstract: A semiconductor device is provided. The semiconductor device comprises a substrate, a gate, a first doped region and a second doped region. The gate is over the substrate. The first doped region and the second doped region are in the substrate. The first doped region and the second doped region are of a same conductivity type and separated by the gate. The length of the first doped region is greater than a length of the second doped region in a direction substantially perpendicular to a channel length defined between the first doped region and the second doped region.Type: ApplicationFiled: May 8, 2020Publication date: August 20, 2020Inventors: Ker-Hsiao HUO, Kong-Beng THEI, Chien-Chih CHOU, Yi-Min CHEN, Chen-Liang CHU
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Patent number: 10748899Abstract: An integrated circuit having an epitaxial source and drain, which reduces gate burnout and increases switching speed so that is suitable for high voltage applications, is provided. The integrated circuit includes a semiconductor substrate having a high voltage N-well (HVNW) and a high voltage P-well (HVPW). The integrated circuit further includes a high-voltage device on the semiconductor substrate. The high-voltage device includes an epitaxial p-type source disposed in the HVNW, an epitaxial p-type drain disposed in the HVPW, and a gate arranged between the epitaxial p-type source and the epitaxial p-type drain on a surface of the semiconductor substrate.Type: GrantFiled: September 26, 2017Date of Patent: August 18, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yi-Huan Chen, Chien-Chih Chou, Kong-Beng Thei
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Publication number: 20200144263Abstract: The present disclosure relates to an integrated circuit (IC) that includes a boundary region defined between a low voltage region, and a method of formation. In some embodiments, the integrated circuit comprises a first gate boundary dielectric layer disposed over a substrate in the low voltage region. A second gate boundary dielectric layer is disposed over the substrate in the high voltage region having a thickness greater than that of the first boundary dielectric layer. The first boundary dielectric layer meets the second boundary dielectric layer at the boundary region. A first polysilicon component is disposed within the boundary region over the first boundary dielectric layer and the second gate boundary layer. A second polysilicon component is disposed within the boundary region over the first polysilicon component. A hard mask component is disposed over the first polysilicon component and laterally neighbored to the second polysilicon component.Type: ApplicationFiled: January 2, 2020Publication date: May 7, 2020Inventors: Yi-Huan Chen, Chien-Chih Chou, Kong-Beng Thei
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Publication number: 20200126870Abstract: Various embodiments of the present disclosure are directed towards a method for forming a fully silicided (FUSI) gated device, the method including: forming a masking layer onto a gate structure over a substrate, the gate structure comprising a polysilicon layer. Forming a first source region and a first drain region on opposing sides of the gate structure within the substrate, the gate structure is formed before the first source and drain regions. Performing a first removal process to remove a portion of the masking layer and expose an upper surface of the polysilicon layer. The first source and drain regions are formed before the first removal process. Forming a conductive layer directly contacting the upper surface of the polysilicon layer. The conductive layer is formed after the first removal process. Converting the conductive layer and polysilicon layer into a FUSI layer. The FUSI layer is thin and uniform in thickness.Type: ApplicationFiled: October 24, 2018Publication date: April 23, 2020Inventors: Yi-Huan Chen, Chien-Chih Chou, Ta-Wei Lin, Hsiao-Chin Tuan, Alexander Kalnitsky, Kong-Beng Thei, Chia-Hong Wu
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Publication number: 20200105748Abstract: In some embodiments, the present disclosure relates to a semiconductor device comprising a source and drain region arranged within a substrate. A conductive gate is disposed over a doped region of the substrate. A gate dielectric layer is disposed between the source region and the drain region and separates the conductive gate from the doped region. A bottommost surface of the gate dielectric layer is below a topmost surface of the substrate. First and second sidewall spacers are arranged along first and second sides of the conductive gate, respectively. An inner portion of the first sidewall spacer and an inner portion of the second sidewall spacer respectively cover a first and second top surface of the gate dielectric layer. A drain extension region and a source extension region respectively separate the drain region and the source region from the gate dielectric layer.Type: ApplicationFiled: May 15, 2019Publication date: April 2, 2020Inventors: Yi-Huan Chen, Chien-Chih Chou, Ta-Wei Lin, Hsiao-Chin Tuan, Alexander Kalnitsky, Kong-Beng Thei, Shi-Chuang Hsiao, Yu-Hong Kuo