Abstract: Scribe lines for increasing a wafer utilizable area are provided. The scribe lines include at least a first scribe line arranged in a first direction in a first gap of a plurality of dies, and at least a second scribe line arranged in the first direction in a second gap of the dies. The first scribe line includes at least an alignment mark or a test key, therefore having a width greater than a width of the second scribe line that is provided for dicing a wafer into a plurality of individual dies. In addition, the scribe lines further include a plurality groups of scribe lines arranged in different directions, and each group of the scribe lines may have various scribe line widths.

Abstract: Scribe lines for increasing a wafer utilizable area are provided. The scribe lines include at least a first scribe line arranged in a first direction in a first gap of a plurality of dies, and at least a second scribe line arranged in the first direction in a second gap of the dies. The first scribe line includes at least an alignment mark or a test key, therefore having a width greater than a width of the second scribe line that is provided for dicing a wafer into a plurality of individual dies. In addition, the scribe lines further include a plurality groups of scribe lines arranged in different directions, and each group of the scribe lines may have various scribe line widths.

Abstract: A NOR type mask ROM includes a plurality of main bit lines formed in parallel with each other, a plurality of first sub-bit lines connected to the main bit lines through bit line contacts, a plurality of T-shaped second sub-bit lines each having a vertical arm formed in parallel with the main bit lines, and a horizontal arm formed in perpendicular with the vertical arm, and a plurality of third sub-bit lines each formed in parallel with the main bit lines and between vertical arms of two neighboring second sub-bit lines.

Abstract: A semiconductor static random access memory (SRAM) device having a noise eliminating means is disclosed. The SRAM device includes a memory cell array, a row detector, a column detector, an address buffer, an access control pulse generator, a sense amplifier and an address transition detector. The address buffer receives an externally issued memory access address for relay to the row decoder for the decode of the row address. The received access address is also relayed to the address transition detector in order to detect the transition status of the address bits of the access address received so as to cause the access control pulse generator to generate a sense amplifier enable signal and a word line enable signal.

Abstract: A process for fabricating memory cells of a static random access memory (SRAM) device is disclosed to reduce the required die area and increase storage capacity. Each of the memory cells of the SRAM comprises a group of four MOS transistors, a pair of resistors, a pair of bit lines, as well as a word line. The process of fabrication the memory cells of the SRAM device comprises a number of process steps that are implemented subsequently on the surface of said semiconductor substrate, with the first and second MOS transistors first formed on the semiconductor substrate. According to the process, the first and second resistors are then formed on top of the first and second MOS transistors. Then the third and fourth MOS transistors and a word line are subsequently formed on top of the first and second resistors. Finally, the first and second bit lines for the memory cells are formed on top of the third and fourth MOS transistors.

Abstract: An static storage cell has 6 FETs, all of the same type. The cells are arrayed in columns that each have a pair of bit lines and rows that each have a word line. Each side of the cell has a pull down FET and a pull up FET and the two sides are interconnected to form a latch. The two nodes where the drain of one pull down FET and the gate of the other pull down FET are connected to the associated bit line through the associated one of two word pass FETs. The gates of the two pull up FETs and the two word pass FETs are connected to the word line. When the word line receives a selection voltage, the pull up FETs are enabled to conduct at a higher current level and the word pass FETs are enabled to apply the bit voltage to the associated node for a write operation or to apply the node voltage to the bit line for a read operation. At other times, the word pass FETs isolate the cell from the bit lines and the pull up FETs conduct at a sufficient current to maintain the latching operation of the cell.

Abstract: A multi-stage sense amplifier for read-only memory having a memory array consisting of a large number of memory cell units. The sense amplifier includes a sense amplifier for sensing the currents flowing through the transistor of the memory cell units of the read-only memory. The memory cell unit transistors are programmed with one of four current capacity characteristics. The sense amplifier also includes three current comparators coupled to the sense amplifier, with each of the comparators having a current comparing unit for comparing the sensed current flowing through the memory cell unit transistors to the current flowing through the comparators. An output of each of the three comparators is provided for identifying whether or not the current of a four capacity characteristics flowing through the memory cell unit transistors is larger than the current flowing through the comparator.

Abstract: A memory redundancy apparatus for replacing defective memory cells in a main memory cell array of a memory device is disclosed. The memory redundancy apparatus operates between two electric potential representing two logic states, and receives a plurality of decoded address signals generated by an input decoding logic to selectively access the redundant memory cells. The memory redundancy apparatus comprises a programmable redundancy decoder logic that receives the address signals and selectively accesses the redundant memory cells to replace the defective memory cells. The memory redundancy apparatus further comprises a redundancy activation circuit coupled to and outputs an activation signal to the programmable redundancy decoder logic so as to activate the operation of the programmable redundancy decoder logic. The disclosed memory redundancy apparatus is capable of zero power consumption when not activated, and the fuse elements necessary to be programmed are relatively few in number.

Abstract: A late programming mask ROM integrated circuit and a process for producing the same. The mask ROM integrated circuit has a silicon substrate, and a plurality of memory cells formed on the silicon substrate. Each memory cell consists of a transistor element and a diode element electrically connected in series. Each transistor element has a drain layer, a channel layer, a source layer all stacked on the silicon substrate in a substantially vertical direction to form an upright drain/channel/source structure region, and a gate electrode region formed on the silicon substrate. The gate electrode regions and the upright drain/channel/source structure regions of the transistor elements are alternately arranged in an adjacent fashion along a substantially horizontal direction. Each diode element is formed by one upright drain/channel/source structure and a diode layer formed on or under the upright drain/channel/source structure.

Abstract: A late programming mask ROM integrated circuit and a process for producing the same. The mask ROM integrated circuit has a silicon substrate, and a plurality of memory cells formed on the silicon substrate. Each memory cell consists of a transistor element and a diode element electrically connected in series. Each transistor element has a drain layer, a channel layer, a source layer all stacked on the silicon substrate in a substantially vertical direction to form an upright drain/channel/source structure region, and a gate electrode region formed on the silicon substrate. The gate electrode regions and the upright drain/channel/source structure regions of the transistor elements are alternately arranged in an adjacent fashion along a substantially horizontal direction. Each diode element is formed by one upright drain/channel/source structure and a diode layer formed on or under the upright drain/channel/source structure.