Patents by Inventor Chien-Chih Sung

Chien-Chih Sung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7535091
    Abstract: A multichip stacking structure is provided, including a chip carrier; a plurality of semiconductor chips stacked on the chip carrier in a stepped manner that an overlying chip mounted on an underlying chip of the plurality of semiconductor chips has a suspended portion free of being in contact with the underlying chip; and a bump mounted on the chip carrier at a position corresponding to a suspended side of the stacked semiconductor chips where the suspended portion of the overlying chip is located. The bump can serve as a blocking member or a filling member to prevent the semiconductor chips from delamination or formation of voids during a molding process.
    Type: Grant
    Filed: April 25, 2006
    Date of Patent: May 19, 2009
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Chien-Chih Sung, Chung-Pao Wang, Yung-Chuan Ku
  • Publication number: 20080305579
    Abstract: A method for fabricating a semiconductor device installed with passive components is provided.
    Type: Application
    Filed: June 5, 2008
    Publication date: December 11, 2008
    Applicant: Siliconware Precision Industries Co., Ltd.
    Inventors: Ming-Shan Lin, Chien-Chih Sung, Chung-Pao Wang, Yung-Chuan Ku, Chien-Chih Chen
  • Publication number: 20080179726
    Abstract: A multi-chip semiconductor package and a method for fabricating the same are disclosed. The method includes electrically connecting a first chip mounted onto a substrate with the substrate through a plurality of first bonding wires; applying an adhesive layer on the substrate at a position proximate to the first chip in a horizontal direction, wherein the adhesive layer at least covers a portion of wireloop of each of the first bonding wires and a first bonding region bonded thereto, such that a second chip overlaps the first bonding region to reduce space wasted on the substrate, thereby allowing more and larger-sized chips to be attached thereon.
    Type: Application
    Filed: January 29, 2008
    Publication date: July 31, 2008
    Applicant: Siliconware Precision Industries Co., Ltd.
    Inventors: Chien-Chih Sung, Chung-Pao Wang
  • Publication number: 20080099902
    Abstract: The present invention provides an insertion-type semiconductor device and a fabrication method thereof, including the steps of: mounting a chip on a BGA substrate and performing a packaging molding process; providing an electrical connecting board formed with a plurality of electrical terminals thereon for allowing the packaged substrate to electrically connect with the electrical terminals on the electrical connecting board via a conductive element thereof; covering a lid to form an insertion-type semiconductor device. As size of the solder pads is much smaller than the electrical terminals of the insertion-type semiconductor device, the area under the semiconductor chip can be reduced to minimize the deformable area of the semiconductor chip when being pressed in the molding process, thereby preventing damage to the semiconductor chip and also meeting the specification requirement of an insertion-type semiconductor device.
    Type: Application
    Filed: February 14, 2007
    Publication date: May 1, 2008
    Applicant: Siliconware Precision Industries Co., Ltd.
    Inventors: Ming-Ke Shih, Ping-Yi Chu, Yong-Liang Chen, Chien-Chih Sung, Chung-Pao Wang
  • Publication number: 20070132084
    Abstract: A multichip stacking structure is provided, including a chip carrier; a plurality of semiconductor chips stacked on the chip carrier in a stepped manner that an overlying chip mounted on an underlying chip of the plurality of semiconductor chips has a suspended portion free of being in contact with the underlying chip; and a bump mounted on the chip carrier at a position corresponding to a suspended side of the stacked semiconductor chips where the suspended portion of the overlying chip is located. The bump can serve as a blocking member or a filling member to prevent the semiconductor chips from delamination or formation of voids during a molding process.
    Type: Application
    Filed: April 25, 2006
    Publication date: June 14, 2007
    Applicant: Siliconware Precision Industries Co., Ltd.
    Inventors: Chien-Chih Sung, Chung-Pao Wang, Yung-Chuan Ku