Patents by Inventor Chien-Chih Wang

Chien-Chih Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240152194
    Abstract: A power consumption reduction method can include defining y operation scenarios according to x types of extracted information, generating z power profiles each used for controlling power provided to a subset of a plurality of processors, assigning the z power profiles to the y operation scenarios in a machine learning model, collecting to-be-evaluated information by the plurality of processors, comparing the to-be-evaluated information with the x types of extracted information to find a most similar type of extracted information, using the machine learning model to select an optimal power profile from the z power profiles according to the most similar type of extracted information, and applying the optimal power profile to control the power provided to the subset of the plurality of processors. The subset of the plurality of processors are of the same type of processor. x, y and z can be an integer larger than zero.
    Type: Application
    Filed: August 18, 2023
    Publication date: May 9, 2024
    Applicant: MEDIATEK INC.
    Inventors: Wen-Wen Hsieh, Ying-Yi Teng, Chien-Chih Wang
  • Publication number: 20240154065
    Abstract: An optoelectronic device includes a first semiconductor layer, a second semiconductor layer and an active layer between the first semiconductor layer and the second semiconductor layer; a first insulating layer on the second semiconductor layer and including a plurality of first openings exposing the first semiconductor layer, wherein the first openings include a first group and a second group; a third electrode on the first insulating layer and including a first extended portion and a second extended portion, wherein the first extended portion and the second extended portion are respectively electrically connected to the first semiconductor layer through the first group of the first openings and the second group of the first openings, and wherein the number of the first group of the first openings is different from the number of the second group of the first openings; and a plurality of fourth electrodes on the second insulating layer and electrically connected to the second semiconductor layer, wherein in a
    Type: Application
    Filed: January 11, 2024
    Publication date: May 9, 2024
    Inventors: Chao-Hsing CHEN, Jia-Kuen WANG, Chien-Chih LIAO, Tzu-Yao TSENG, Tsun-Kai KO, Chien-Fu SHEN
  • Patent number: 11961777
    Abstract: A package structure and a method of forming the same are provided. The package structure includes a first die, a second die, a first encapsulant, and a buffer layer. The first die and the second die are disposed side by side. The first encapsulant encapsulates the first die and the second die. The second die includes a die stack encapsulated by a second encapsulant encapsulating a die stack. The buffer layer is disposed between the first encapsulant and the second encapsulant and covers at least a sidewall of the second die and disposed between the first encapsulant and the second encapsulant. The buffer layer has a Young's modulus less than a Young's modulus of the first encapsulant and a Young's modulus of the second encapsulant.
    Type: Grant
    Filed: June 27, 2022
    Date of Patent: April 16, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Chih Chen, Chien-Hsun Lee, Chung-Shi Liu, Hao-Cheng Hou, Hung-Jui Kuo, Jung-Wei Cheng, Tsung-Ding Wang, Yu-Hsiang Hu, Sih-Hao Liao
  • Publication number: 20240119200
    Abstract: A method of building a characteristic model includes: acquiring raw electrical data from a measurement system outside one or more processing units; acquiring operational state-related data from an information collector inside the one or more processing units; performing a data annealing process on the raw electrical data and the operational state-related data to obtain and purified electrical data and purified operational state-related data; and performing a machine learning (ML)-based process to build the characteristic model based on the purified electrical data and the purified operational state-related data.
    Type: Application
    Filed: October 3, 2023
    Publication date: April 11, 2024
    Applicant: MEDIATEK INC.
    Inventors: Yu-Jen Chen, Chien-Chih Wang, Wen-Wen Hsieh, Ying-Yi Teng
  • Publication number: 20240111337
    Abstract: An electronic device including a body and a receptacle connector is provided. The body has a side wall surface, a receptacle slot located at the side wall surface, a waterproof protrusion protruding from the side wall surface, and two gutters located at the side wall surface, where the waterproof protrusion is located above the receptacle slot, and the two gutters are respectively located at two opposite sides of the receptacle slot. The receptacle connector is disposed in the receptacle slot.
    Type: Application
    Filed: May 8, 2023
    Publication date: April 4, 2024
    Applicant: Acer Incorporated
    Inventors: Wei-Chih Wang, Chen-Min Hsiu, Chien-Yu Lee, Szu-Wei Yang, Fang-Ying Huang
  • Patent number: 11941741
    Abstract: A graphics system includes an effect engine and a graphics pipeline. The graphics pipeline performs pipeline operations on graphical objects in a frame. The graphics pipeline includes at least a fragment shader stage. An application programming interface (API) provides an instruction that specifies a subset of the graphical objects in the frame for the effect engine to execute. When detecting the instruction, the graphics pipeline invokes the effect engine to perform a predefined set of graphics operations on the subset of the graphical objects in the frame. The predefined set of graphics operations has a higher computational complexity than the pipeline operations.
    Type: Grant
    Filed: March 30, 2022
    Date of Patent: March 26, 2024
    Assignee: MediaTek Inc.
    Inventors: Chien-Chih Wang, Ying-Chieh Chen
  • Patent number: 11937932
    Abstract: An acute kidney injury predicting system and a method thereof are proposed. A processor reads the data to be tested, the detection data, the machine learning algorithm and the risk probability comparison table from a main memory. The processor trains the detection data according to the machine learning algorithm to generate an acute kidney injury prediction model, and inputs the data to be tested into the acute kidney injury prediction model to generate an acute kidney injury characteristic risk probability and a data sequence table. The data sequence table lists the data to be tested in sequence according to a proportion of each of the data to be tested in the acute kidney injury characteristics. The processor selects one of the medical treatment data from the risk probability comparison table according to the acute kidney injury characteristic risk probability.
    Type: Grant
    Filed: July 8, 2022
    Date of Patent: March 26, 2024
    Assignees: TAICHUNG VETERANS GENERAL HOSPITAL, TUNGHAI UNIVERSITY
    Inventors: Chieh-Liang Wu, Chun-Te Huang, Cheng-Hsu Chen, Tsai-Jung Wang, Kai-Chih Pai, Chun-Ming Lai, Min-Shian Wang, Ruey-Kai Sheu, Lun-Chi Chen, Yan-Nan Lin, Chien-Lun Liao, Ta-Chun Hung, Chien-Chung Huang, Chia-Tien Hsu, Shang-Feng Tsai
  • Patent number: 11940828
    Abstract: A voltage tracking circuit is provided. The voltage tracking circuit includes first and second P-type transistors and a control circuit. The drain of the first P-type transistor is coupled to a first voltage terminal. The gate and the drain of the second P-type transistor are respectively coupled to the first voltage terminal and a second voltage terminal. The control circuit is coupled to the first and second voltage terminals and generates a control voltage according to the first voltage and the second voltage. The sources of the first and second P-type transistors are coupled to an output terminal of the voltage tracking circuit, and the output voltage is generated at the output terminal. In response to the second voltage being higher than the first voltage, the control circuit generates the control signal to turn off the first P-type transistor.
    Type: Grant
    Filed: August 17, 2022
    Date of Patent: March 26, 2024
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Shao-Chang Huang, Yeh-Ning Jou, Ching-Ho Li, Kai-Chieh Hsu, Chun-Chih Chen, Chien-Wei Wang, Gong-Kai Lin, Li-Fan Chen
  • Publication number: 20220222885
    Abstract: A graphics system includes an effect engine and a graphics pipeline. The graphics pipeline performs pipeline operations on graphical objects in a frame. The graphics pipeline includes at least a fragment shader stage. An application programming interface (API) provides an instruction that specifies a subset of the graphical objects in the frame for the effect engine to execute. When detecting the instruction, the graphics pipeline invokes the effect engine to perform a predefined set of graphics operations on the subset of the graphical objects in the frame. The predefined set of graphics operations has a higher computational complexity than the pipeline operations.
    Type: Application
    Filed: March 30, 2022
    Publication date: July 14, 2022
    Inventors: Chien-Chih Wang, Ying-Chieh Chen
  • Patent number: 11321901
    Abstract: A graphics system includes an effect engine, which executes a predefined set of graphics operations having a higher computational complexity than pipeline operations. The graphics system further includes a graphics pipeline operative to perform the pipeline operations on graphical objects in a frame. The effect engine is operative to execute the predefined set of graphics operations on a subset of the graphical objects in the frame. One or more buffers are operative to receive pixels of the frame for display. The frame includes the graphical objects operated on by the graphics pipeline and the subset of the graphical objects operated on by the effect engine.
    Type: Grant
    Filed: February 13, 2020
    Date of Patent: May 3, 2022
    Assignee: MediaTek Inc.
    Inventors: Chien-Chih Wang, Ying-Chieh Chen
  • Publication number: 20210256753
    Abstract: A graphics system includes an effect engine, which executes a predefined set of graphics operations having a higher computational complexity than pipeline operations. The graphics system further includes a graphics pipeline operative to perform the pipeline operations on graphical objects in a frame. The effect engine is operative to execute the predefined set of graphics operations on a subset of the graphical objects in the frame. One or more buffers are operative to receive pixels of the frame for display. The frame includes the graphical objects operated on by the graphics pipeline and the subset of the graphical objects operated on by the effect engine.
    Type: Application
    Filed: February 13, 2020
    Publication date: August 19, 2021
    Inventors: Chien-Chih Wang, Ying-Chieh Chen
  • Patent number: 10985168
    Abstract: A semiconductor memory device includes a substrate, at least one floating gate electrode, an interlayer dielectric layer, an interconnection structure, an etching stop layer, a conductive structure, and an opening. The floating gate electrode is disposed on the substrate. The interlayer dielectric layer is disposed on the floating gate electrode. The interconnection structure is disposed in the interlayer dielectric layer. The etching stop layer is disposed on the interlayer dielectric layer. The conductive structure penetrates the etching stop layer and is electrically connected with the interconnection structure. The opening penetrates the etching stop layer and overlaps at least a part of the floating gate electrode in a thickness direction of the substrate.
    Type: Grant
    Filed: October 1, 2019
    Date of Patent: April 20, 2021
    Assignee: United Semiconductor (Xiamen) Co., Ltd.
    Inventors: Jung-Chun Yen, Chien-Chih Wang, Guang Yang, Jiawei Lyu, Linshan Yuan, Wen Yi Tan
  • Publication number: 20210066322
    Abstract: A semiconductor memory device includes a substrate, at least one floating gate electrode, an interlayer dielectric layer, an interconnection structure, an etching stop layer, a conductive structure, and an opening. The floating gate electrode is disposed on the substrate. The interlayer dielectric layer is disposed on the floating gate electrode. The interconnection structure is disposed in the interlayer dielectric layer. The etching stop layer is disposed on the interlayer dielectric layer. The conductive structure penetrates the etching stop layer and is electrically connected with the interconnection structure. The opening penetrates the etching stop layer and overlaps at least a part of the floating gate electrode in a thickness direction of the substrate.
    Type: Application
    Filed: October 1, 2019
    Publication date: March 4, 2021
    Inventors: Jung-Chun Yen, Chien-Chih Wang, Guang Yang, JIAWEI LYU, LINSHAN YUAN, WEN YI TAN
  • Patent number: 10210046
    Abstract: A computer system includes a memory unit and a processing unit. The memory unit is configured to store a default setting value with an image file form. The processing unit is electrically connected to the memory unit, and configured to read the default setting value with the image file form from the memory unit. When the computer system is unable to be activated, the processing unit is configured to trigger the computer system to activate a safe mode of a basic input/output system, and to compare the default setting value with a system setting value of the computer system to generate a comparison result, so as to adjust and reactivate the computer system according to the comparison result.
    Type: Grant
    Filed: March 24, 2017
    Date of Patent: February 19, 2019
    Assignees: Inventec (Pudong) Technology Corporation, INVENTEC CORPORATION
    Inventors: Chien-Chih Wang, Yung-Sheng Chiang
  • Publication number: 20180150358
    Abstract: A computer system includes a memory unit and a processing unit. The memory unit is configured to store a default setting value with an image file form. The processing unit is electrically connected to the memory unit, and configured to read the default setting value with the image file form from the memory unit. When the computer system is unable to be activated, the processing unit is configured to trigger the computer system to activate a safe mode of a basic input/output system, and to compare the default setting value with a system setting value of the computer system to generate a comparison result, so as to adjust and reactivate the computer system according to the comparison result.
    Type: Application
    Filed: March 24, 2017
    Publication date: May 31, 2018
    Inventors: Chien-Chih WANG, Yung-Sheng CHIANG
  • Patent number: 8802358
    Abstract: A method of forming an alignment film is provided. A photosensitive polymer material is provided, wherein the photosensitive polymer material defines a first pixel area and a second pixel area respectively defining a first sub-pixel area and the second sub-pixel area. In a first exposure, the photosensitive polymer material is irradiate by a first exposure light and a second exposure light to form a first alignment portion and a second alignment portion with different alignment directions in the first sub-pixel of the first pixel area and the second sub-pixel of the second pixel area respectively. In a second exposure, the photosensitive polymer material is irradiated with the first exposure light and the second exposure light to form a third alignment portion and a fourth alignment portion with different alignment directions in the first sub-pixel of the second pixel area and the second sub-pixel of the first pixel area respectively.
    Type: Grant
    Filed: November 6, 2012
    Date of Patent: August 12, 2014
    Assignees: Innocom Technology (Shenzhen) Co., Ltd., Innolux Corporation
    Inventors: Yao-Jen Ou, Han-Lang Lee, Chien-Chih Wang, Hung-I Tseng
  • Patent number: 8736787
    Abstract: A liquid crystal panel module, a backlight module and a liquid crystal display (LCD) are provided. The liquid crystal panel module includes a liquid crystal panel and a diffraction grating layer. The liquid crystal panel has a plurality of pixels. The diffraction grating layer is disposed on the liquid crystal panel, and a maximum period of a grating of the diffraction grating layer is smaller than 1/10 of a size of the pixels. The backlight module includes a light guide plate, a light emitting element and a diffraction grating film. A light provided by the light emitting element emits from a light emitting surface of the light guide plate and is bended towards the light emitting element after passing through the diffraction grating film. The liquid crystal panel module and the backlight module can be applied to the LCD together or individually.
    Type: Grant
    Filed: January 6, 2011
    Date of Patent: May 27, 2014
    Assignees: Chimei Innolux Corporation, Chi Mei Corporation, Klaser Technology, Inc.
    Inventors: Wang-Yang Li, Hung-Yu Lin, Hsin-Wen Chang, Yi-Pan Liang, Chien-Chih Wang, Wai-Hon Lee, Hua-Fang Tsai
  • Publication number: 20110187964
    Abstract: A liquid crystal panel module, a backlight module and a liquid crystal display (LCD) are provided. The liquid crystal panel module includes a liquid crystal panel and a diffraction grating layer. The liquid crystal panel has a plurality of pixels. The diffraction grating layer is disposed on the liquid crystal panel, and a maximum period of a grating of the diffraction grating layer is smaller than 1/10 of a size of the pixels. The backlight module includes a light guide plate, a light emitting element and a diffraction grating film. A light provided by the light emitting element emits from a light emitting surface of the light guide plate and is bended towards the light emitting element after passing through the diffraction grating film. The liquid crystal panel module and the backlight module can be applied to the LCD together or individually.
    Type: Application
    Filed: January 6, 2011
    Publication date: August 4, 2011
    Applicants: CHIMEI INNOLUX CORPORATION, CHI MEI CORPORATION, KLASER TECHNOLOGY INC.
    Inventors: Wang-Yang LI, Hung-Yu LIN, Hsin-Wen CHANG, Yi-Pan LIANG, Chien-Chih WANG, Wai-Hon LEE, Huai-Fang TSAI
  • Patent number: 7576702
    Abstract: An automatic feedback adjustment device for a digital antenna includes a digital antenna unit, a trafficator, a tuner, a demodulator, an antenna direction driver unit, a secondary controller, and a primary controller. The digital antenna unit is a digital video/broadcasting antenna system. The trafficator is connected to the digital antenna unit to retrieve direction data associated with the actual elevation angle and direction. The tuner is connected to the digital antenna unit and the demodulator is connected to the tuner in order to receive and convert a transmission signal from a transmission terminal into the video data and a received-signal quality signal. The antenna direction driver unit is connected to the digital antenna unit in order to drive adjustment of direction and elevation angle of the antenna.
    Type: Grant
    Filed: May 11, 2007
    Date of Patent: August 18, 2009
    Assignee: Genesys Logic, Inc.
    Inventors: Hsin-Ching Yin, Wen-Ming Huang, Wen-Fu Tsai, Ching-Chun Huang, Chi-Wei Hsiao, Jin-Min Lin, Chien-Chih Wang
  • Publication number: 20070245385
    Abstract: An automatic feedback adjustment device for a digital antenna includes a digital antenna unit, a trafficator, a tuner, a demodulator, an antenna direction driver unit, a secondary controller, and a primary controller. The digital antenna unit is a digital video/broadcasting antenna system. The trafficator is connected to the digital antenna unit to retrieve direction data associated with the actual elevation angle and direction. The tuner is connected to the digital antenna unit and the demodulator is connected to the tuner in order to receive and convert a transmission signal from a transmission terminal into the video data and a received-signal quality signal. The antenna direction driver unit is connected to the digital antenna unit in order to drive adjustment of direction and elevation angle of the antenna.
    Type: Application
    Filed: May 11, 2007
    Publication date: October 18, 2007
    Inventors: Hsin-Ching Yin, Wen-Ming Huang, Wen-Fu Tsai, Ching-Chun Huang, Chi-Wei Hsiao, Jin-Min Lin, Chien-Chih Wang