Abstract: A layer stack including a first bonding dielectric material layer, a dielectric metal oxide layer, and a second bonding dielectric material layer is formed over a top surface of a substrate including a substrate semiconductor layer. A conductive material layer is formed by depositing a conductive material over the second bonding dielectric material layer. The substrate semiconductor layer is thinned by removing portions of the substrate semiconductor layer that are distal from the layer stack, whereby a remaining portion of the substrate semiconductor layer includes a top semiconductor layer. A semiconductor device may be formed on the top semiconductor layer.

Abstract: A slide rail assembly comprises a first rail, a second rail and a handle. When the handle is moved from a first operating position to a second operating position, the handle is configured to unlock the second rail relative to the first rail at a predetermined position.

Abstract: A slide rail assembly includes a first rail, a second rail, a third rail, a fourth rail and a fifth rail. The second rail and the third rail are respectively movable relative to the first rail. Each of the second rail and the third rail is formed with a passage. The fourth rail and the fifth rail are configured to be accommodated in the passages of the second rail and the third rail respectively.

Abstract: A dummy gate electrode and a dummy gate dielectric are removed to form a recess between adjacent gate spacers. A gate dielectric is deposited in the recess, and a barrier layer is deposited over the gate dielectric. A first work function layer is deposited over the barrier layer. A first anti-reaction layer is formed over the first work function layer, the first anti-reaction layer reducing oxidation of the first work function layer. A fill material is deposited over the first anti-reaction layer.

Abstract: A semiconductor package includes a semiconductor die having a first surface and a second surface opposite to the first surface, a conductive wiring layer stacked with the semiconductor die and proximal to the first surface, an encapsulant encapsulating the semiconductor die and stacked with the conductive wiring layer, and a replacement structure exposing from the encapsulant and being free of fillers. A method for manufacturing the semiconductor package is also disclosed in the present disclosure.

Abstract: A semiconductor package includes a semiconductor die having a first surface and a second surface opposite to the first surface, a conductive wiring layer stacked with the semiconductor die and proximal to the first surface, an encapsulant encapsulating the semiconductor die and stacked with the conductive wiring layer, and a replacement structure exposing from the encapsulant and being free of fillers. A method for manufacturing the semiconductor package is also disclosed in the present disclosure.

Abstract: An electronic device includes an insulating layer, a metal layer and at least one electrical connecting element. The insulating layer has a top surface and a bottom surface opposite to the top surface, and defines an opening extending between the top surface and the bottom surface. The metal layer is disposed in the opening of the insulating layer and has a top surface and a bottom surface opposite to the top surface. The bottom surface of the metal layer is substantially coplanar with the bottom surface of the insulating layer. The electrical connecting element is attached to the bottom surface of the metal layer through a seed layer.

Abstract: An electronic device includes an insulating layer, a metal layer and at least one electrical connecting element. The insulating layer has a top surface and a bottom surface opposite to the top surface, and defines an opening extending between the top surface and the bottom surface. The metal layer is disposed in the opening of the insulating layer and has a top surface and a bottom surface opposite to the top surface. The bottom surface of the metal layer is substantially coplanar with the bottom surface of the insulating layer. The electrical connecting element is attached to the bottom surface of the metal layer through a seed layer.

Abstract: The invention relates to an aqueous cleaning composition for use in a cleaning process during or after a chemical mechanical planarization for a copper integrated circuit processing, comprising 0.05 to 20 wt % of a nitrogen-containing heterocyclic organic base, 0.05 to 50 wt % of an alcohol amine, 0.01-10 wt % of a quaternary ammonium hydroxide, and water. When used during or after the planarization process, the inventive cleaning composition of the invention can effectively remove residual contaminants from the surfaces of the wafers and simultaneously maintain a good surface roughness of the wafers.

Abstract: The invention relates to an aqueous cleaning composition for wafers with copper wires that have been treated by chemical mechanical planarization in an integrated circuit processing, comprising 0.1 to 15 wt % of a nitrogen-containing heterocyclic organic base, 0.1 to 35 wt % of an alcohol amine and water. Upon contact with copper-containing semiconductor wafers that have been treated by chemical mechanical planarization for an effective period of time, the aqueous cleaning composition can effectively remove residual contaminants from the surfaces of the wafers, and simultaneously provide the copper-containing semiconductor wafers with a better surface roughness.

Abstract: An aqueous cleaning composition for cleaning wafer contaminants after a chemical mechanical planarization process, includes: 0.1-20 wt % of an alkanolamine selected from the group consisting of 2-amino-1,3-propanediol, 2-amino-2-(hydroxymethyl)-1,3-propanediol, and combinations thereof; 0.05-20 wt % of a quaternary amine; and water. The cleaning composition is capable of removing efficiently residual contaminants from a polished surface of a wafer and imparting the wafer with a better surface roughness.

Abstract: The invention relates to an aqueous cleaning composition for use in a cleaning process during or after a chemical mechanical planarization for a copper integrated circuit processing, comprising 0.05 to 20 wt % of a nitrogen-containing heterocyclic organic base, 0.05 to 50 wt % of an alcohol amine, 0.01-10 wt % of a quaternary ammonium hydroxide, and water. When used during or after the planarization process, the inventive cleaning composition of the invention can effectively remove residual contaminants from the surfaces of the wafers and simultaneously maintain a good surface roughness of the wafers.

Abstract: An auto cycled pipeline system includes a plurality of main pipes, a plurality of cycle pipes, and a plurality of control values. The plurality of main pipes arranged in parallel and used to pump the fluid, and one side of each main pipe is connected to an inlet pipe, the other side of each main pipe is connected to an exit pipe. Each main pipe has a check value and a cycle pipe. One side of each cycle pipe is attached to a foregoing joint in front of the check value and the other side is attached to a rearward joint behind the check value of each main pipe. And each cycle pipe has a control value. The stagnant fluid in the stopped main pipe can be cycled by the cycle pipe of the pipeline system automatically, to prevent deterioration and to keep the purity of the fluid in the pipeline system.