Patents by Inventor Chien Ching Chen

Chien Ching Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240171161
    Abstract: A frequency calibration (FCAL) circuit and a method for calibrating an oscillation frequency of a controllable oscillator are provided. The FCAL circuit includes the controllable oscillator, a divider, a time-to-digital converter (TDC) and a calibration logic. The controllable oscillator generates a controllable oscillation clock according to a calibration code. The divider divides the oscillation frequency of the controllable oscillation clock by a predetermined divisor to generate a divided clock. The TDC converts a first period between first edges of a reference clock and the divided clock into a first period code and converts a second period between second edges of the reference clock and the divided clock into a second period code. The calibration logic compares the first period code and the second period code to generate a comparison result for determining whether the first period is greater or less than the second period, and accordingly controls the calibration code.
    Type: Application
    Filed: July 18, 2023
    Publication date: May 23, 2024
    Applicant: MEDIATEK INC.
    Inventors: Chien-Wei Chen, Kairen Fong, Chao-Ching Hung, Yu-Li Hsueh
  • Patent number: 11978740
    Abstract: A layer stack including a first bonding dielectric material layer, a dielectric metal oxide layer, and a second bonding dielectric material layer is formed over a top surface of a substrate including a substrate semiconductor layer. A conductive material layer is formed by depositing a conductive material over the second bonding dielectric material layer. The substrate semiconductor layer is thinned by removing portions of the substrate semiconductor layer that are distal from the layer stack, whereby a remaining portion of the substrate semiconductor layer includes a top semiconductor layer. A semiconductor device may be formed on the top semiconductor layer.
    Type: Grant
    Filed: February 17, 2022
    Date of Patent: May 7, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Harry-Hak-Lay Chuang, Kuo-Ching Huang, Wei-Cheng Wu, Hsin Fu Lin, Henry Wang, Chien Hung Liu, Tsung-Hao Yeh, Hsien Jung Chen
  • Publication number: 20240136346
    Abstract: A semiconductor die package includes an inductor-capacitor (LC) semiconductor die that is directly bonded with a logic semiconductor die. The LC semiconductor die includes inductors and capacitors that are integrated into a single die. The inductors and capacitors of the LC semiconductor die may be electrically connected with transistors and other logic components on the logic semiconductor die to form a voltage regulator circuit of the semiconductor die package. The integration of passive components (e.g., the inductors and capacitors) of the voltage regulator circuit into a single semiconductor die reduces signal propagation distances in the voltage regulator circuit, which may increase the operating efficiency of the voltage regulator circuit, may reduce the formfactor for the semiconductor die package, may reduce parasitic capacitance and/or may reduce parasitic inductance in the voltage regulator circuit (thereby improving the performance of the voltage regulator circuit), among other examples.
    Type: Application
    Filed: April 17, 2023
    Publication date: April 25, 2024
    Inventors: Chien Hung LIU, Yu-Sheng CHEN, Yi Ching ONG, Hsien Jung CHEN, Kuen-Yi CHEN, Kuo-Ching HUANG, Harry-HakLay CHUANG, Wei-Cheng WU, Yu-Jen WANG
  • Publication number: 20240114272
    Abstract: A speaker device is installed in an electronic device, and the speaker device includes a speaker module and a first loop tube. The speaker module has a casing and a speaker unit. The casing has a main sound cavity and a sound outlet. The speaker unit is disposed in the casing, and the speaker unit includes a diaphragm, which is communicated with the sound outlet. The first loop tube has a first end and a second end, and the first end is connected to the casing. The length of the first loop tube is at least 10 mm, and the inner diameter of the first loop tube is at least 2 mm.
    Type: Application
    Filed: April 18, 2023
    Publication date: April 4, 2024
    Inventors: Jia-Ren CHANG, Ruey-Ching SHYU, Chien-Chung CHEN
  • Publication number: 20240101784
    Abstract: A novel additive for recycling thermoset materials, its related recyclable thermoset composition and its application are disclosed. Specifically, the composition of the additive comprises at least one copolymer that has at least one carbamate group, at least one carbonate group and/or at least one urea group, and a number-average molecular weight of the copolymer is between 100 and 50,000 Da.
    Type: Application
    Filed: September 5, 2023
    Publication date: March 28, 2024
    Inventors: Chien-Hsin Wu, Ying-Chi Huang, Ying-Feng Lin, Wen-Chang Chen, Ho-Ching Huang, Ru-Jong Jeng
  • Publication number: 20240105644
    Abstract: A semiconductor die package includes a high dielectric constant (high-k) dielectric layer over a device region of a first semiconductor die that is bonded with a second semiconductor die in a wafer on wafer (WoW) configuration. A through silicon via (TSV) structure may be formed through the device region. The high-k dielectric layer has an intrinsic negative charge polarity that provides a coupling voltage to modify the electric potential in the device region. In particular, the electron carriers in high-k dielectric layer attracts hole charge carriers in device region, which suppresses trap-assist tunnels that result from surface defects formed during etching of the recess for the TSV structure. Accordingly, the high-k dielectric layer described herein reduces the likelihood of (and/or the magnitude of) current leakage in semiconductor devices that are included in the device region of the first semiconductor die.
    Type: Application
    Filed: January 6, 2023
    Publication date: March 28, 2024
    Inventors: Tsung-Hao YEH, Chien Hung LIU, Hsien Jung CHEN, Hsin Heng WANG, Kuo-Ching HUANG
  • Publication number: 20240088026
    Abstract: A semiconductor device according to embodiments of the present disclosure includes a first die including a first bonding layer and a second die including a second hybrid bonding layer. The first bonding layer includes a first dielectric layer and a first metal coil embedded in the first dielectric layer. The second bonding layer includes a second dielectric layer and a second metal coil embedded in the second dielectric layer. The second hybrid bonding layer is bonded to the first hybrid bonding layer such that the first dielectric layer is bonded to the second dielectric layer and the first metal coil is bonded to the second metal coil.
    Type: Application
    Filed: January 17, 2023
    Publication date: March 14, 2024
    Inventors: Yi Ching Ong, Wei-Cheng Wu, Chien Hung Liu, Harry-Haklay Chuang, Yu-Sheng Chen, Yu-Jen Wang, Kuo-Ching Huang
  • Patent number: 11913597
    Abstract: A product-display system for displaying and securing a retail product. The system may include a retainer having a retainer bracket and a retainer body coupled to the retainer bracket. A retaining cable may be coupled to the retainer body at an opening in the retainer body. A fastener that may be unfastened to release the product from the retainer may only be accessed through the opening of the retainer body such that when the retaining cable is coupled to the opening, no fasteners of the retainer may be visible or accessible. The system may also include a display stem for holding the retainer and product. The display stem may include a recess for receiving at least a portion of the retainer body. The retaining cable may extend through the display stem and may simultaneously transmit power and data to a displayed product. The retainer may be returned to and held on top of the display stem using a retaining cable.
    Type: Grant
    Filed: December 1, 2021
    Date of Patent: February 27, 2024
    Assignee: Apple Inc.
    Inventors: Sheng Yang, Eric W. Wang, Steven C. Michalske, Olivia Ching, Clayton R. Woosley, Samuel Wing Man Yuen, Paul Joseph Hack, Ricardo A Mariano, Chien Tsun Chen, George Tziviskos, Charles A. Schwalbach
  • Patent number: 11217498
    Abstract: A semiconductor package includes a semiconductor die having a first surface and a second surface opposite to the first surface, a conductive wiring layer stacked with the semiconductor die and proximal to the first surface, an encapsulant encapsulating the semiconductor die and stacked with the conductive wiring layer, and a replacement structure exposing from the encapsulant and being free of fillers. A method for manufacturing the semiconductor package is also disclosed in the present disclosure.
    Type: Grant
    Filed: November 1, 2019
    Date of Patent: January 4, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Hsu-Nan Fang, Chien-Ching Chen, Chen Yuan Weng
  • Publication number: 20210134692
    Abstract: A semiconductor package includes a semiconductor die having a first surface and a second surface opposite to the first surface, a conductive wiring layer stacked with the semiconductor die and proximal to the first surface, an encapsulant encapsulating the semiconductor die and stacked with the conductive wiring layer, and a replacement structure exposing from the encapsulant and being free of fillers. A method for manufacturing the semiconductor package is also disclosed in the present disclosure.
    Type: Application
    Filed: November 1, 2019
    Publication date: May 6, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Hsu-Nan FANG, Chien-Ching CHEN, Chen Yuan WENG
  • Patent number: 10573572
    Abstract: An electronic device includes an insulating layer, a metal layer and at least one electrical connecting element. The insulating layer has a top surface and a bottom surface opposite to the top surface, and defines an opening extending between the top surface and the bottom surface. The metal layer is disposed in the opening of the insulating layer and has a top surface and a bottom surface opposite to the top surface. The bottom surface of the metal layer is substantially coplanar with the bottom surface of the insulating layer. The electrical connecting element is attached to the bottom surface of the metal layer through a seed layer.
    Type: Grant
    Filed: July 19, 2018
    Date of Patent: February 25, 2020
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Hsu-Nan Fang, Chien-Ching Chen
  • Publication number: 20200027804
    Abstract: An electronic device includes an insulating layer, a metal layer and at least one electrical connecting element. The insulating layer has a top surface and a bottom surface opposite to the top surface, and defines an opening extending between the top surface and the bottom surface. The metal layer is disposed in the opening of the insulating layer and has a top surface and a bottom surface opposite to the top surface. The bottom surface of the metal layer is substantially coplanar with the bottom surface of the insulating layer. The electrical connecting element is attached to the bottom surface of the metal layer through a seed layer.
    Type: Application
    Filed: July 19, 2018
    Publication date: January 23, 2020
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Hsu-Nan FANG, Chien-Ching CHEN
  • Patent number: 8067352
    Abstract: The invention relates to an aqueous cleaning composition for use in a cleaning process during or after a chemical mechanical planarization for a copper integrated circuit processing, comprising 0.05 to 20 wt % of a nitrogen-containing heterocyclic organic base, 0.05 to 50 wt % of an alcohol amine, 0.01-10 wt % of a quaternary ammonium hydroxide, and water. When used during or after the planarization process, the inventive cleaning composition of the invention can effectively remove residual contaminants from the surfaces of the wafers and simultaneously maintain a good surface roughness of the wafers.
    Type: Grant
    Filed: March 14, 2008
    Date of Patent: November 29, 2011
    Assignee: Epoch Material Co., Ltd.
    Inventors: Chien Ching Chen, Wen Cheng Liu, Tsung Hsien Chuang, Jui Ching Chen
  • Patent number: 8063006
    Abstract: The invention relates to an aqueous cleaning composition for wafers with copper wires that have been treated by chemical mechanical planarization in an integrated circuit processing, comprising 0.1 to 15 wt % of a nitrogen-containing heterocyclic organic base, 0.1 to 35 wt % of an alcohol amine and water. Upon contact with copper-containing semiconductor wafers that have been treated by chemical mechanical planarization for an effective period of time, the aqueous cleaning composition can effectively remove residual contaminants from the surfaces of the wafers, and simultaneously provide the copper-containing semiconductor wafers with a better surface roughness.
    Type: Grant
    Filed: May 18, 2006
    Date of Patent: November 22, 2011
    Assignee: Epoch Material Co., Ltd.
    Inventors: Chien Ching Chen, Wen Cheng Liu, Jing-Chiuan Shiue, Teng Yan Huo
  • Publication number: 20090170742
    Abstract: An aqueous cleaning composition for cleaning wafer contaminants after a chemical mechanical planarization process, includes: 0.1-20 wt % of an alkanolamine selected from the group consisting of 2-amino-1,3-propanediol, 2-amino-2-(hydroxymethyl)-1,3-propanediol, and combinations thereof; 0.05-20 wt % of a quaternary amine; and water. The cleaning composition is capable of removing efficiently residual contaminants from a polished surface of a wafer and imparting the wafer with a better surface roughness.
    Type: Application
    Filed: August 19, 2008
    Publication date: July 2, 2009
    Applicant: EPOCH MATERIAL CO., LTD.
    Inventors: Tsung-Hsien Chuang, Chien-Ching Chen, Wen-Cheng Liu
  • Publication number: 20090036343
    Abstract: The invention relates to an aqueous cleaning composition for use in a cleaning process during or after a chemical mechanical planarization for a copper integrated circuit processing, comprising 0.05 to 20 wt % of a nitrogen-containing heterocyclic organic base, 0.05 to 50 wt % of an alcohol amine, 0.01-10 wt % of a quaternary ammonium hydroxide, and water. When used during or after the planarization process, the inventive cleaning composition of the invention can effectively remove residual contaminants from the surfaces of the wafers and simultaneously maintain a good surface roughness of the wafers.
    Type: Application
    Filed: March 14, 2008
    Publication date: February 5, 2009
    Applicant: Epoch Material Co., Ltd.
    Inventors: Chien Ching Chen, Wen Cheng Liu, Tsung Hsien Chuang, Jui Ching Chen
  • Publication number: 20050139269
    Abstract: An auto cycled pipeline system includes a plurality of main pipes, a plurality of cycle pipes, and a plurality of control values. The plurality of main pipes arranged in parallel and used to pump the fluid, and one side of each main pipe is connected to an inlet pipe, the other side of each main pipe is connected to an exit pipe. Each main pipe has a check value and a cycle pipe. One side of each cycle pipe is attached to a foregoing joint in front of the check value and the other side is attached to a rearward joint behind the check value of each main pipe. And each cycle pipe has a control value. The stagnant fluid in the stopped main pipe can be cycled by the cycle pipe of the pipeline system automatically, to prevent deterioration and to keep the purity of the fluid in the pipeline system.
    Type: Application
    Filed: December 29, 2003
    Publication date: June 30, 2005
    Applicant: SiS Microelectronics Corporation
    Inventor: Chien-Ching Chen