Patents by Inventor Chien-Ching Wu

Chien-Ching Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11978740
    Abstract: A layer stack including a first bonding dielectric material layer, a dielectric metal oxide layer, and a second bonding dielectric material layer is formed over a top surface of a substrate including a substrate semiconductor layer. A conductive material layer is formed by depositing a conductive material over the second bonding dielectric material layer. The substrate semiconductor layer is thinned by removing portions of the substrate semiconductor layer that are distal from the layer stack, whereby a remaining portion of the substrate semiconductor layer includes a top semiconductor layer. A semiconductor device may be formed on the top semiconductor layer.
    Type: Grant
    Filed: February 17, 2022
    Date of Patent: May 7, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Harry-Hak-Lay Chuang, Kuo-Ching Huang, Wei-Cheng Wu, Hsin Fu Lin, Henry Wang, Chien Hung Liu, Tsung-Hao Yeh, Hsien Jung Chen
  • Publication number: 20240136346
    Abstract: A semiconductor die package includes an inductor-capacitor (LC) semiconductor die that is directly bonded with a logic semiconductor die. The LC semiconductor die includes inductors and capacitors that are integrated into a single die. The inductors and capacitors of the LC semiconductor die may be electrically connected with transistors and other logic components on the logic semiconductor die to form a voltage regulator circuit of the semiconductor die package. The integration of passive components (e.g., the inductors and capacitors) of the voltage regulator circuit into a single semiconductor die reduces signal propagation distances in the voltage regulator circuit, which may increase the operating efficiency of the voltage regulator circuit, may reduce the formfactor for the semiconductor die package, may reduce parasitic capacitance and/or may reduce parasitic inductance in the voltage regulator circuit (thereby improving the performance of the voltage regulator circuit), among other examples.
    Type: Application
    Filed: April 17, 2023
    Publication date: April 25, 2024
    Inventors: Chien Hung LIU, Yu-Sheng CHEN, Yi Ching ONG, Hsien Jung CHEN, Kuen-Yi CHEN, Kuo-Ching HUANG, Harry-HakLay CHUANG, Wei-Cheng WU, Yu-Jen WANG
  • Publication number: 20240101784
    Abstract: A novel additive for recycling thermoset materials, its related recyclable thermoset composition and its application are disclosed. Specifically, the composition of the additive comprises at least one copolymer that has at least one carbamate group, at least one carbonate group and/or at least one urea group, and a number-average molecular weight of the copolymer is between 100 and 50,000 Da.
    Type: Application
    Filed: September 5, 2023
    Publication date: March 28, 2024
    Inventors: Chien-Hsin Wu, Ying-Chi Huang, Ying-Feng Lin, Wen-Chang Chen, Ho-Ching Huang, Ru-Jong Jeng
  • Publication number: 20240088026
    Abstract: A semiconductor device according to embodiments of the present disclosure includes a first die including a first bonding layer and a second die including a second hybrid bonding layer. The first bonding layer includes a first dielectric layer and a first metal coil embedded in the first dielectric layer. The second bonding layer includes a second dielectric layer and a second metal coil embedded in the second dielectric layer. The second hybrid bonding layer is bonded to the first hybrid bonding layer such that the first dielectric layer is bonded to the second dielectric layer and the first metal coil is bonded to the second metal coil.
    Type: Application
    Filed: January 17, 2023
    Publication date: March 14, 2024
    Inventors: Yi Ching Ong, Wei-Cheng Wu, Chien Hung Liu, Harry-Haklay Chuang, Yu-Sheng Chen, Yu-Jen Wang, Kuo-Ching Huang
  • Publication number: 20240072432
    Abstract: An ultra-wideband antenna device is disposed on a casing of an electronic device. The ultra-wideband antenna device includes radio frequency terminals, a first antenna module, a second antenna module, and a switch module. The radio frequency terminals, the first antenna module and the switch module are located in the casing. The first antenna module is located on a metal frame of the casing, and the first antenna module includes a first antenna. The second antenna module includes a second antenna, a third antenna, and a fourth antenna. The switch module is connected between the radio frequency terminals and the first antenna module. When the switch module turns on one of the radio frequency terminals and the first antenna for distance measurement, the switch module selectively turns on at least one of the second antenna, the third antenna, or the fourth antenna.
    Type: Application
    Filed: March 28, 2023
    Publication date: February 29, 2024
    Inventors: Yu-Ching WU, Chien-Ming HSU
  • Publication number: 20220057720
    Abstract: Lithographic patterning method for creating features on a surface of a substrate, including the steps of: applying a resist material to the surface; performing resist processing steps, including at least: selectively exposing the resist material layer to a surface treatment step, wherein the resist material in the exposed locations is chemically modified; and developing the resist material layer to selectively remove the resist material locally. The method further comprises detecting, during or after the resist processing steps, a chemical modification of the resist material for monitoring or evaluating the processing steps. The step of detecting is performed by scanning the surface using a scanning probe microscopy device, and wherein the scanning includes contacting the surface with the probe tip in a probing area. The probing area coincides with at least one location of the exposed locations and non-exposed locations, for detecting the chemical modification. The document further describes a system.
    Type: Application
    Filed: December 13, 2019
    Publication date: February 24, 2022
    Inventors: Diederik Jan MAAS, Jacques Cor Johan VAN DER DONCK, Maarten Hubertus VAN ES, Chien-Ching WU, Klara MATUROVA, Robert Wilhelm WILLEKERS
  • Publication number: 20040083643
    Abstract: A flying safety net device has a first post, a second post, a main net, a first main rope, a center rope, a second main rope, a first lateral rope, a second lateral rope, a first main loop, a second main loop, a third main loop, a fourth main loop, a first auxiliary loop, and a second auxiliary loop. The main net has a plurality of upper fringe thread sections, a plurality of lower fringe thread sections, a large number of netting thread sections, a large number of netting loops, and a large number of meshes. The first main rope passes through the upper fringe thread sections of the main net. The second main rope passes through the lower fringe thread sections of the main net. The center rope passes through a middle portion of the main net.
    Type: Application
    Filed: January 21, 2003
    Publication date: May 6, 2004
    Inventor: Chien-Ching Wu