Abstract: A display device is disclosed. A display panel displays a first image according to a first output image. A timing controller includes a receiving unit, a compression unit, a decompression unit and a processing unit. The receiving unit receives a first input image and a second input image and outputs a first processed image and a second processed image. The first input image is the same as the first processed image. The second input image is the same as the second processed image. The compression unit generates a first compressed image according to the first processed image. The receiving unit stores the first compressed image. The decompression unit processes the stored first compressed image to generate a first decompressed image. The processing unit processes the second processed image and the first decompressed image to generate the first output image.

Abstract: An image display system includes a data driving circuit, a gate driving circuit and a controller chip. The data driving circuit outputs a plurality of data driving signals to provide a display image signal to a plurality of pixels on a pixel array. The gate driving circuit outputs a plurality of gate driving signals to drive the pixels on the pixel array. The controller chip receives an input image signal which includes a plurality of sub-frame data, recombines the plurality of sub-frame data so that more than one of the plurality of sub-frame data of the input image signal are merged as one single frame data, and generates and outputs the display image signal.

Abstract: A display device is disclosed. A display panel displays a first image according to a first output image. A timing controller includes a receiving unit, a compression unit, a decompression unit and a processing unit. The receiving unit receives a first input image and a second input image and outputs a first processed image and a second processed image. The first input image is the same as the first processed image. The second input image is the same as the second processed image. The compression unit generates a first compressed image according to the first processed image. The receiving unit stores the first compressed image. The decompression unit processes the stored first compressed image to generate a first decompressed image. The processing unit processes the second processed image and the first decompressed image to generate the first output image.

Abstract: A display device including a display panel and a timing controller is disclosed. The display panel displays an image according to an output image. The timing controller includes a receiving unit, a first transformation unit, a second transformation unit and a processing unit. The receiving unit generates a processing image and a read-out image according to a first input image and a second input image. The first transformation unit transforms the processing image to generate a first transformed image. The second transformation unit transforms the read-out image to generate a second transformed image. The processing unit processes the first and the second transformed images to generate the output image. A resolution of the processing image and a resolution of the read-out image are less than a resolution of the display panel.

Abstract: A transmission circuit has a dispatching circuit and a calculating circuit. The transmission circuit is between a processing circuit and a memory controller. The processor is connected to the dispatching circuit via a first signal line. The dispatching circuit is connected to the calculating circuit via a second signal line. The calculating circuit is connected to the memory controller via a third signal line. Besides, a fast signal line is provided for connecting the dispatching circuit and the memory controller. During operation, the processing circuit transmits a data stream to the dispatching circuit. The dispatching circuit checks whether a speed-up condition is satisfied. If the speed-up condition is not satisfied, the data stream follows a conventional path through the calculating circuit. If the speed-up condition is satisfied, the data stream is directly transmitted to the memory controller and such design increases the performance of the transmission circuit.

Abstract: A transmission circuit has a dispatching circuit and a calculating circuit. The transmission circuit is between a processing circuit and a memory controller. The processor is connected to the dispatching circuit via a first signal line. The dispatching circuit is connected to the calculating circuit via a second signal line. The calculating circuit is connected to the memory controller via a third signal line. Besides, a fast signal line is provided for connecting the dispatching circuit and the memory controller. During operation, the processing circuit transmits a data stream to the dispatching circuit. The dispatching circuit checks whether a speed-up condition is satisfied. If the speed-up condition is not satisfied, the data stream follows a conventional path through the calculating circuit. If the speed-up condition is satisfied, the data stream is directly transmitted to the memory controller and such design increases the performance of the transmission circuit.