Patents by Inventor Chien-Chou TSENG

Chien-Chou TSENG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • ELECTRONIC DEVICE AND METHOD OF MANUFACTURING ELECTRONIC DEVICE
    Publication number: 20230154877
    Abstract: An electronic device includes a substrate, an electronic component, a first interposing layer and a second interposing layer. The substrate is non-planar and the substrate includes a first substrate pad and a second substrate pad. The electronic component includes a first component pad and a second component pad corresponding to the first substrate pad and the second substrate pad respectively. When the first component pad contacts the first substrate pad, a height difference exists between the second component pad and the second substrate pad. The first interposing layer connects between the first component pad and the first substrate pad. The second interposing layer connects between the second component pad and the second substrate pad. A thickness difference between the first interposing layer and the second interposing layer is 0.5 to 1 time the height difference.
    Type: Application
    Filed: March 24, 2022
    Publication date: May 18, 2023
    Applicant: Industrial Technology Research Institute
    Inventors: Yu-Ming Peng, Chien-Chou Tseng, Chih-Chia Chang, Kuan-Chu Wu, Yu-Lin Hsu
  • Panel to be plated, electroplating process using the same, and chip manufactured from the same
    Patent number: 10941498
    Abstract: A panel to be plated is provided. The panel includes a substrate and an electric field compensation structure. The substrate includes a plurality of units to be plated each including a first pattern to be plated. The electric field compensation structure is disposed on the substrate. The electric field compensation structure includes a second pattern to be plated surrounding at least one of the units to be plated. A ratio of an area of the first pattern to be plated of the units to be plated to an area of the second pattern to be plated of the electric field compensation structure is in a range from 1:0.07 to 1:0.3.
    Type: Grant
    Filed: June 20, 2019
    Date of Patent: March 9, 2021
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Chien-Hsun Chu, Chien-Chou Tseng, Ming-Huan Yang, Tai-Jui Wang, Yu-Hua Chung, Chieh-Wei Feng
  • PANEL TO BE PLATED, ELECTROPLATING PROCESS USING THE SAME, AND CHIP MANUFACTURED FROM THE SAME
    Publication number: 20200063282
    Abstract: A panel to be plated is provided. The panel includes a substrate and an electric field compensation structure. The substrate includes a plurality of units to be plated each including a first pattern to be plated. The electric field compensation structure is disposed on the substrate. The electric field compensation structure includes a second pattern to be plated surrounding at least one of the units to be plated. A ratio of an area of the first pattern to be plated of the units to be plated to an area of the second pattern to be plated of the electric field compensation structure is in a range from 1:0.07 to 1:0.3.
    Type: Application
    Filed: June 20, 2019
    Publication date: February 27, 2020
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Chien-Hsun CHU, Chien-Chou TSENG, Ming-Huan YANG, Tai-Jui WANG, Yu-Hua CHUNG, Chieh-Wei FENG