Abstract: A memory device, includes a memory array for storing a plurality of vector data each of which has an MSB vector and a LSB vector. The memory array includes a plurality of memory units each of which has a first bit and a second bit. The first bit is used to store the MSB vector of each vector data, the second bit is used to store the LSB vector of each vector data. A bit line corresponding to each vector data executes one time of bit-line-setup, and reads the MSB vector and the LSB vector of each vector data according to the bit line. The threshold voltage distribution of each memory unit is divided into N states, where N is a positive integer and N is less than 2 to the power of 2, and the effective bit number stored by each memory unit is less than 2.

Abstract: A memory device, includes a memory array for storing a plurality of vector data each of which has an MSB vector and a LSB vector. The memory array includes a plurality of memory units each of which has a first bit and a second bit. The first bit is used to store the MSB vector of each vector data, the second bit is used to store the LSB vector of each vector data. Each vector data is executed with a multiplying-operation, the MSB vector and the LSB vector of each vector data is executed with a first group-counting operation and a second group-counting operation respectively. The threshold voltage distribution of each memory unit is divided into N states, where N is a positive integer and N is less than 2 to the power of 2, the effective bit number stored by each memory unit is less than 2.

Abstract: A memory device, includes a memory array for storing a plurality of vector data each of which has an MSB vector and a LSB vector. The memory array includes a plurality of memory units each of which has a first bit and a second bit. The first bit is used to store the MSB vector of each vector data, the second bit is used to store the LSB vector of each vector data. A bit line corresponding to each vector data executes one time of bit-line-setup, and reads the MSB vector and the LSB vector of each vector data according to the bit line. The threshold voltage distribution of each memory unit is divided into N states, where N is a positive integer and N is less than 2 to the power of 2, and the effective bit number stored by each memory unit is less than 2.

Abstract: A memory device includes: a memory array used for implementing neural networks (NN); and a controller coupled to the memory array. The controller is configured for: in updating and writing unrewritable data into the memory array in a training phase, marching the unrewritable data into a buffer zone of the memory array; and in updating and writing rewritable data into the memory array in the training phase, marching the rewritable data by skipping the buffer zone.

Abstract: A memory device includes: a memory array used for implementing neural networks (NN), the NN including a plurality of layers; and a controller coupled to the memory array, the controller being configured for: determining a computation duration of a first data of a first layer of the plurality of layers; selecting a first program operation if the computation duration of the first data of the first layer is shorter than a threshold; and selecting a second program operation if the computation duration of the first data of the first layer is longer than the threshold, wherein the second program operation has a longer program pulse time than the first program operation.

Abstract: An in-memory computing method and apparatus, adapted for a processor to perform MAC operations on a memory, are provided. In the method, a format of binary data of weights is transformed from a floating-point format into a quantized format by truncating at least a portion of fraction bits of the binary data and calculating complements of remaining bits, and programming the transformed binary data into cells of the memory. A tuning procedure is performed by iteratively inputting binary data of input signals into the memory, integrating outputs of the memory, and adjusting the weights programmed to the cells based on the integrated outputs. The binary data of the weights is reshaped based on a probability of reducing bits with a value of one in the binary data of each weight. The tuning procedure is repeated until an end condition is met.

Abstract: An operation method of an artificial neural network is provided. The operation method includes: dividing input information into a plurality of sub-input information, and expanding kernel information to generate expanded kernel information; performing a Fast Fourier Transform (FFT) on the sub-input information and the expanded kernel information to respectively generate a plurality of frequency domain sub-input information and frequency domain expanded kernel information; respectively performing a multiplying operation on the frequency domain expanded kernel information and the frequency domain sub-input information to respectively generate a plurality of sub-feature maps; and performing an inverse FFT on the sub-feature maps to provide a plurality of converted sub-feature maps for executing a feature extraction operation of the artificial neural network.

Abstract: A memory data management method includes the following steps reading a plurality of data of a plurality of memory cells of a memory block; determining whether error bits of the data exceed an error correction code (ECC) threshold; if the error bits of the data exceed the ECC threshold, a programming process being executed to increase a first threshold voltage of a first state data of the data for exceeding a first threshold, to increase a second threshold voltage of a second state data of the data for exceeding a second threshold, and to increase a third threshold voltage of a third state data of the data for exceeding a third threshold.

Abstract: A memory data management method includes the following steps: reading a plurality of data of a plurality of memory cells of a memory block; determining whether error bits of the data exceed an error correction code (ECC) threshold; if the error bits of the data exceed the ECC threshold, a programming process being executed to enhance a first state data of the data for exceeding a first threshold, to enhance a second state data of the data for exceeding a second threshold, and to enhance a third state data of the data for exceeding a third threshold.

Abstract: A memory device includes: a memory array used for implementing neural networks (NN); and a controller coupled to the memory array. The controller is configured for: in updating and writing unrewritable data into the memory array in a training phase, marching the unrewritable data into a buffer zone of the memory array; and in updating and writing rewritable data into the memory array in the training phase, marching the rewritable data by skipping the buffer zone.

Abstract: A memory device includes: a memory array used for implementing neural networks (NN), the NN including a plurality of layers; and a controller coupled to the memory array, the controller being configured for: determining a computation duration of a first data of a first layer of the plurality of layers; selecting a first program operation if the computation duration of the first data of the first layer is shorter than a threshold; and selecting a second program operation if the computation duration of the first data of the first layer is longer than the threshold, wherein the second program operation has a longer program pulse time than the first program operation.

Abstract: An erasing method and a memory device are provided. The memory device includes a plurality of memory blocks. Each of the memory blocks has n sub-blocks. The erasing method includes the following steps. A first erase region is selected from a first memory block of the memory blocks, and the first erase region includes at least one sub-block. A sub-block erase operation is performed on the first erase region of the first memory block.

Abstract: An erasing method and a memory device are provided. The memory device includes a plurality of memory blocks. Each of the memory blocks has n sub-blocks. The erasing method includes the following steps. A first erase region is selected from a first memory block of the memory blocks, and the first erase region includes at least one sub-block. A sub-block erase operation is performed on the first erase region of the first memory block.