Patents by Inventor Chien-Chung Lin

Chien-Chung Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210098695
    Abstract: A method includes forming Magnetic Tunnel Junction (MTJ) stack layers, which includes depositing a bottom electrode layer; depositing a bottom magnetic electrode layer over the bottom electrode layer; depositing a tunnel barrier layer over the bottom magnetic electrode layer; depositing a top magnetic electrode layer over the tunnel barrier layer; and depositing a top electrode layer over the top magnetic electrode layer. The method further includes patterning the MTJ stack layers to form a MTJ; and performing a passivation process on a sidewall of the MTJ to form a protection layer. The passivation process includes reacting sidewall surface portions of the MTJ with a process gas comprising elements selected from the group consisting of oxygen, nitrogen, carbon, and combinations thereof.
    Type: Application
    Filed: December 14, 2020
    Publication date: April 1, 2021
    Inventors: Tai-Yen Peng, Yu-Shu Chen, Sin-Yi Yang, Chen-Jung Wang, Chien Chung Huang, Han-Ting Lin, Jyu-Horng Shieh, Qiang Fu
  • Patent number: 10964004
    Abstract: The present invention is an automated optical inspection method using deep learning, comprising the steps of: providing a plurality of paired image combinations, wherein each said paired image combination includes at least one defect-free image and at least one defect-containing image corresponding to the defect-free image; providing a convolutional neural network to start a training mode of the convolutional neural network; inputting the plurality of paired image combinations into the convolutional neural network, and adjusting a weight of at least one fully connected layer of the convolutional neural network through backpropagation to complete the training mode of the convolutional neural network; and performing an optical inspection process using the trained convolutional neural network.
    Type: Grant
    Filed: December 14, 2018
    Date of Patent: March 30, 2021
    Assignee: UTECHZONE CO., LTD.
    Inventors: Chih-Heng Fang, Chia-Liang Lu, Ming-Tang Hsu, Arulmurugan Ambikapathi, Chien-Chung Lin
  • Patent number: 10963019
    Abstract: An electronic device includes a first body, a second body, two hinges, and at least one electronic assembly. The two hinges are connected between the first body and the second body, and the first body and the second body are adapted to rotate relatively through the two hinges. The electronic assembly is connected to the second body and is located between the two hinges.
    Type: Grant
    Filed: January 21, 2020
    Date of Patent: March 30, 2021
    Assignee: COMPAL ELECTRONICS, INC.
    Inventors: Ming-Chung Peng, Ko-Fan Chen, Chun-Yi Ho, Chien-Ting Lin, Yu-Jung Liu, Hsin-Jung Lee, Hsin-Yu Huang, Jih-Houng Lee, Ming-Feng Liu, Kuo-Jung Wu, Kuo-Pin Chen, Chia-Ling Lee, Jing-Jie Lin
  • Publication number: 20210081274
    Abstract: A memory data management method includes the following steps: reading a plurality of data of a plurality of memory cells of a memory block; determining whether error bits of the data exceed an error correction code (ECC) threshold; if the error bits of the data exceed the ECC threshold, a programming process being executed to enhance a first state data of the data for exceeding a first threshold, to enhance a second state data of the data for exceeding a second threshold, and to enhance a third state data of the data for exceeding a third threshold.
    Type: Application
    Filed: September 16, 2019
    Publication date: March 18, 2021
    Inventors: Yung-Chun LI, Ping-Hsien LIN, Kun-Chi CHIANG, Chien-Chung HO
  • Patent number: 10952341
    Abstract: A casing of an electronic device including a metallic housing, a first non-conductive spacer and a second non-conductive spacer is provided. The metallic housing has an inner surface and an outer surface opposite to the inner surface, and the outer surface has a back side and lateral sides connecting with the back side. The inner surface is substantially a recessed structure. The metallic housing having a first gap and a second gap substantially located at two opposite ends of the metallic housing and being parallel with each other. The first non-conductive spacer is disposed the first gap, and the second non-conductive spacer is disposed in the second gap.
    Type: Grant
    Filed: June 9, 2020
    Date of Patent: March 16, 2021
    Assignee: HTC Corporation
    Inventors: Tim Chung-Ting Wu, Cheng-Chieh Chuang, Chi-Jen Lu, Chun-Lung Chu, Chien-Hung Lin
  • Publication number: 20210076522
    Abstract: A metallic housing of an electronic device including an inner surface, an outer surface and a first non-conductive spacer is provided. The outer surface is opposite to the inner surface, and the outer surface has a back side and lateral sides connecting with the back side. The inner surface is substantially a recessed structure. The metallic housing having a first gap and a second gap substantially located at two opposite ends of the metallic housing and being parallel with each other. The first gap and the second gap each communicates the inner surface and the outer surface. The first non-conductive spacer is disposed the first gap of the metallic housing.
    Type: Application
    Filed: November 17, 2020
    Publication date: March 11, 2021
    Applicant: HTC Corporation
    Inventors: Tim Chung-Ting Wu, Cheng-Chieh Chuang, Chi-Jen Lu, Chun-Lung Chu, Chien-Hung Lin
  • Publication number: 20210074909
    Abstract: The present disclosure provides a method for manufacturing semiconductor structure, including forming an insulation layer, forming a first via trench in the insulation layer, forming a barrier layer in the first via trench, forming a bottom electrode via in the first via trench, forming a magnetic tunneling junction (MTJ) layer above the bottom electrode via, and performing an ion beam etching operation, including patterning the MTJ layer to form an MTJ and removing a portion of the insulation layer from a top surface.
    Type: Application
    Filed: November 24, 2020
    Publication date: March 11, 2021
    Inventors: TAI-YEN PENG, YU-SHU CHEN, CHIEN CHUNG HUANG, SIN-YI YANG, CHEN-JUNG WANG, HAN-TING LIN, JYU-HORNG SHIEH, QIANG FU
  • Patent number: 10935874
    Abstract: An illumination system and a projection device are provided. The illumination system includes at least one laser light source providing at least one laser beam and a polarizing rotation module including a first axle, a first driving element, and a polarizing element. The first axle has a first revolution frequency. The polarizing element is disposed on a transmission path of the laser beam. The first driving element causes the polarizing element to rotate in a temporally sequenced manner. When the polarizing element is rotated, the laser beam is transmitted to the polarizing element at a specific frequency in a plurality of first time periods. The laser beam passing through the polarizing element has different polarizing states at different times. The specific frequency and the first revolution frequency of the first axle are not exactly divisible by each other. The invention can generate an image with uniform polarizing direction.
    Type: Grant
    Filed: November 14, 2019
    Date of Patent: March 2, 2021
    Assignee: Coretronic Corporation
    Inventors: Yao-Shun Lin, Haw-Woei Pan, Chi-Tang Hsieh, Chien-Chung Liao
  • Publication number: 20210050923
    Abstract: Provided is a rapid over-the-air (OTA) production line test platform, including a device under test (DUT), an antenna array and two reflecting plates. The DUT has a beamforming function. The antenna array is arranged opposite to the DUT, and emits beams with beamforming. Two reflecting plates are disposed opposite to each other, and are arranged between the DUT and the antenna array. The beam OTA test of the DUT is carried out by propagation of the beams between the antenna array, the DUT and the two reflecting plates. Accordingly, the test time can be greatly shortened and the cost of test can be effectively reduced. In addition to the above-mentioned rapid OTA production line test platform, platforms for performing the OTA production line test by using horn antenna arrays together with bending waveguides and using a 3D elliptic curve are also provided.
    Type: Application
    Filed: August 14, 2020
    Publication date: February 18, 2021
    Inventors: Su-Wei Chang, Chueh-Jen Lin, Wen-Tsai Tsai, Shun-Chung Kuo, Yang Tai, Wei-Yang Chen, Chien-Tse Fang, Po-Chia Huang, Jiun-Wei Wu, Yu-Cheng Lin
  • Publication number: 20210043161
    Abstract: A cursor image detection comparison and feedback status determination method is disclosed. The method is based on a non-invasive data-extraction system architecture, and uses an image processing unit to perform detection comparison on a cursor image shown on an operation screen outputted from a machine controller. The method includes steps of obtaining cursor foreground and background images set by a user, and selecting an algorithm to process the cursor foreground and background images to generate a cursor mask, and reading a cursor image and applying the cursor mask on the cursor image for pattern comparison, transmitting information of a comparison result and a cursor feedback status to a software control system, so as to provide a correction system to perform a cursor process program and check whether the movement of the cursor meet a position controlled by a feedback and correction system, thereby completing closed-loop control for the cursor.
    Type: Application
    Filed: August 8, 2019
    Publication date: February 11, 2021
    Inventors: Chao-Tung YANG, Wei-Hung CHEN, Shih-Hsun LIN, Wei-Jyun TU, Chun-Hong LIU, Chien-Chung LIN, Chieh-Yuan LO, Hsiao-Ling CHANG
  • Publication number: 20200412280
    Abstract: An apparatus and a method for monitoring the relative relationship between the wafer and the chuck is provided, especially for monitoring whether the wafer is sticky on the chuck when the wafer is de-chucked. The lift pins may be extended outside the chuck to separate the wafer and the chuck when the wafer is de-chucked. By detecting the capacitance between the de-chucked wafer and the chuck, especially by comparing the detected capacitance with the capacitance that the wafer is held by the chuck, one may determine whether the wafer is sticky on the chuck, or even whether the wafer is properly supported by the lift pins. Accordingly, an early alarm may be issued if the wafer is sticky or improperly removed. Besides, by controlling a switch electrically connected to a lift pin that contacted the wafer, the charges at the wafer may be eliminated.
    Type: Application
    Filed: September 10, 2020
    Publication date: December 31, 2020
    Inventors: Te-Min Wang, Yu-Ho Ni, Chun-Chieh Lin, Chien-Chung Hou, Cheng-Mao Chien
  • Patent number: 10878559
    Abstract: A method for evaluating an efficiency of a manual inspection for a defect pattern is provided according to an embodiment of the disclosure, which comprises: enabling an evaluation program; loading a test image automatically by the enabled evaluation program and displaying the test image in a user interface; detecting a user behavior of a user after the user watches the test image; generating original data according to the user behavior, wherein the original data reflects at least one of whether the user identifies the defect pattern in the test image and a type of the defect pattern identified by the user; and performing a quantitative operation on the original data to generate evaluation data corresponding to the efficiency of the manual inspection, wherein the evaluation data reflects an evaluation result corresponding to the efficiency of the manual inspection.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: December 29, 2020
    Assignee: UTECHZONE CO., LTD.
    Inventors: Chia-Chun Tsou, Arulmurugan Ambikapathi, Chien-Chung Lin
  • Patent number: 10868239
    Abstract: A method includes forming Magnetic Tunnel Junction (MTJ) stack layers, which includes depositing a bottom electrode layer; depositing a bottom magnetic electrode layer over the bottom electrode layer; depositing a tunnel barrier layer over the bottom magnetic electrode layer; depositing a top magnetic electrode layer over the tunnel barrier layer; and depositing a top electrode layer over the top magnetic electrode layer. The method further includes patterning the MTJ stack layers to form a MTJ; and performing a passivation process on a sidewall of the MTJ to form a protection layer. The passivation process includes reacting sidewall surface portions of the MTJ with a process gas comprising elements selected from the group consisting of oxygen, nitrogen, carbon, and combinations thereof.
    Type: Grant
    Filed: October 25, 2018
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tai-Yen Peng, Yu-Shu Chen, Sin-Yi Yang, Chen-Jung Wang, Chien Chung Huang, Han-Ting Lin, Jyu-Horng Shieh, Qiang Fu
  • Publication number: 20200387200
    Abstract: An electronic device includes a first body, a second body, two hinges, and at least one electronic assembly. The two hinges are connected between the first body and the second body, and the first body and the second body are adapted to rotate relatively through the two hinges. The electronic assembly is connected to the second body and is located between the two hinges.
    Type: Application
    Filed: January 21, 2020
    Publication date: December 10, 2020
    Applicant: COMPAL ELECTRONICS, INC.
    Inventors: Ming-Chung Peng, Ko-Fan Chen, Chun-Yi Ho, Chien-Ting Lin, Yu-Jung Liu, Hsin-Jung Lee, Hsin-Yu Huang, Jih-Houng Lee, Ming-Feng Liu, Kuo-Jung Wu, Kuo-Pin Chen, Chia-Ling Lee, Jing-Jie Lin
  • Patent number: 10862023
    Abstract: The present disclosure provides a semiconductor structure, including a bottom electrode via, a top surface of the bottom electrode via having a first width, a barrier layer surrounding the bottom electrode via, and a magnetic tunneling junction (MTJ) over the bottom electrode via, a bottom of the MTJ having a second width, the first width being narrower than the second width.
    Type: Grant
    Filed: January 8, 2019
    Date of Patent: December 8, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Tai-Yen Peng, Yu-Shu Chen, Chien Chung Huang, Sin-Yi Yang, Chen-Jung Wang, Han-Ting Lin, Jyu-Horng Shieh, Qiang Fu
  • Patent number: 10804234
    Abstract: The present disclosure, in some embodiments, relates to a semiconductor structure. The semiconductor structure includes a substrate and a first conductive pad arranged over the substrate. A boundary structure is on an upper surface of the substrate around the first conductive pad. The boundary structure has one or more sidewalls defining an opening with a round shape over the first conductive pad.
    Type: Grant
    Filed: April 12, 2019
    Date of Patent: October 13, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chien Ling Hwang, Yeong-Jyh Lin, Bor-Ping Jang, Hsiao-Chung Liang
  • Patent number: 10804821
    Abstract: An apparatus and a method for monitoring the relative relationship between the wafer and the chuck is provided, especially for monitoring whether the wafer is sticky on the chuck when the wafer is de-chucked. The lift pins may be extended outside the chuck to separate the wafer and the chuck when the wafer is de-chucked. By detecting the capacitance between the de-chucked wafer and the chuck, especially by comparing the detected capacitance with the capacitance that the wafer is held by the chuck, one may determine whether the wafer is sticky on the chuck, or even whether the wafer is properly supported by the lift pins. Accordingly, an early alarm may be issued if the wafer is sticky or improperly removed. Besides, by controlling a switch electrically connected to a lift pin that contacted the wafer, the charges at the wafer may be eliminated.
    Type: Grant
    Filed: August 29, 2017
    Date of Patent: October 13, 2020
    Assignee: ADVANCED ION BEAM TECHNOLOGY, INC.
    Inventors: Te-Min Wang, Yu-Ho Ni, Chun-Chieh Lin, Chien-Chung Hou, Cheng-Mao Chien
  • Patent number: D902981
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: November 24, 2020
    Assignee: TDK TAIWAN CORP.
    Inventors: Fu-Yuan Wu, Kun-Shih Lin, Shang-Yu Hsu, Yi-Ho Chen, Shih-Ting Huang, Shou-Jen Liu, Chien-Lun Huang, Yi-Hsin Nieh, Chen-Chi Kuo, Chia-Pin Hsu, Yu-Huai Liao, Shin-Hua Chen, Yu-Cheng Lin, Shao-Chung Chang, Kuo-Chun Kao, Chia-Hsiu Liu, Chao-Chun Chang, Yuan-Shih Liao
  • Patent number: D902982
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: November 24, 2020
    Assignee: TDK TAIWAN CORP.
    Inventors: Fu-Yuan Wu, Kun-Shih Lin, Shang-Yu Hsu, Yi-Ho Chen, Shih-Ting Huang, Shou-Jen Liu, Chien-Lun Huang, Yi-Hsin Nieh, Chen-Chi Kuo, Chia-Pin Hsu, Yu-Huai Liao, Shin-Hua Chen, Yu-Cheng Lin, Shao-Chung Chang, Kuo-Chun Kao, Chia-Hsiu Liu, Chao-Chun Chang, Yuan-Shih Liao
  • Patent number: D908775
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: January 26, 2021
    Assignee: TDK Taiwan Corp.
    Inventors: Fu-Yuan Wu, Kun-Shih Lin, Shang-Yu Hsu, Yi-Ho Chen, Shih-Ting Huang, Shou-Jen Liu, Chien-Lun Huang, Yi-Hsin Nieh, Chen-Chi Kuo, Chia-Pin Hsu, Yu-Huai Liao, Shin-Hua Chen, Yu-Cheng Lin, Shao-Chung Chang, Kuo-Chun Kao, Chia-Hsiu Liu, Chao-Chun Chang, Yuan-Shih Liao