Abstract: A structure of semiconductor device is provided, including a first circuit structure, formed on a first substrate. A first test pad is disposed on the first substrate. A second circuit structure is formed on a second substrate. A second test pad is disposed on the second substrate. A first bonding pad of the first circuit structure is bonded to a second bonding pad of the second circuit structure. One of the first test pad and the second test pad is an inner pad while another one of the first test pad and the second test pad is an outer pad, wherein the outer pad surrounds the inner pad.

Abstract: A structure of semiconductor device is provided, including a first circuit structure, formed on a first substrate. A first test pad is disposed on the first substrate. A second circuit structure is formed on a second substrate. A second test pad is disposed on the second substrate. A first bonding pad of the first circuit structure is bonded to a second bonding pad of the second circuit structure. One of the first test pad and the second test pad is an inner pad while another one of the first test pad and the second test pad is an outer pad, wherein the outer pad surrounds the inner pad.

Abstract: A structure of semiconductor device is provided, including a first circuit structure, formed on a first substrate. A first test pad is disposed on the first substrate. A second circuit structure is formed on a second substrate. A second test pad is disposed on the second substrate. A first bonding pad of the first circuit structure is bonded to a second bonding pad of the second circuit structure. One of the first test pad and the second test pad is an inner pad while another one of the first test pad and the second test pad is an outer pad, wherein the outer pad surrounds the inner pad.

Abstract: A photodetector includes a substrate, at least one nanowire and a cladding layer. The at least one nanowire is disposed on the substrate and has a semiconductor core. The cladding layer is disposed on sidewalls of the semiconductor core and includes an epitaxial semiconductor film in contact with the sidewalls of the semiconductor core, a metal film disposed on the outside of the epitaxial semiconductor film and a high-k material layer disposed on the outside of metal film.

Abstract: A photodetector includes a substrate, at least one nanowire and a cladding layer. The at least one nanowire is disposed on the substrate and has a semiconductor core. The cladding layer is disposed on sidewalls of the semiconductor core and includes an epitaxial semiconductor film in contact with the sidewalls of the semiconductor core, a metal film disposed on the outside of the epitaxial semiconductor film and a high-k material layer disposed on the outside of metal film.

Abstract: A wafer level packaging method includes the following steps. A first wafer is bonded over a second wafer. A first grinding process on the first wafer is performed, to remove an upper chamfered edge of the first wafer and reduce a thickness of the first wafer. A trimming process is performed on the first wafer, to remove a lower chamfered edge of the first wafer to form a trimmed first wafer. A second grinding process is performed on the trimmed first wafer, to reduce a thickness of the trimmed first wafer.

Abstract: A stacked semiconductor device is provided, including a first semiconductor structure, a second semiconductor structure and a bonding structure disposed between the first and second semiconductor structures. The first semiconductor structure and the second semiconductor structure include first conductive pillars and second conductive pillars, respectively. The first semiconductor structure is stacked above the second semiconductor structure. The bonding structure contacts the first conductive pillars and the second conductive pillars, wherein the bonding structure comprises conductive paths for electrically connecting the first conductive pillars and the second conductive pillars.

Abstract: A wafer level packaging method includes the following steps. A first wafer is bonded over a second wafer. A first grinding process on the first wafer is performed, to remove an upper chamfered edge of the first wafer and reduce a thickness of the first wafer. A trimming process is performed on the first wafer, to remove a lower chamfered edge of the first wafer to form a trimmed first wafer. A second grinding process is performed on the trimmed first wafer, to reduce a thickness of the trimmed first wafer.

Abstract: A stacked semiconductor structure includes a first wafer, a second wafer, a first insulting layer, and a second insulating layer. The first wafer includes a first front surface, a first back surface, and a first interconnection structure. The first interconnection structure includes at least a first top metal layer exposed on the first front surface of the first wafer. The second wafer includes a second front surface, a second back surface, and a second interconnection structure. The second interconnection structure includes at least a second top metal layer exposed on the second front surface of the second wafer. The first insulating layer is formed on the first front surface of the first wafer, and the second insulating layer is formed on the second front surface of the second wafer. The first insulating layer and the second insulating layer contact each other.

Abstract: The present invention relates to a CMOS image sensor device and a method of forming the same. The CMOS image sensor device includes a substrate, a deep trench isolation (DTI), a photodiode, an electrode and an interface region. The DTI and the photodiode are both disposed in the substrate. The electrode is disposed on the DTI. The interface region is formed adjacent to the DTI.

Abstract: A method of making a gate structure includes the following steps. First, a gate is formed. Then, a first silicon oxide layer, a silicon nitride layer, and a second silicon oxide layer are formed to cover the gate from bottom to top. Later, a dry etching is performed to etch the second silicon oxide layer. After that, a wet etching is performed to etch the silicon nitride layer and the first silicon oxide layer. The aforesaid wet etching is performed by utilizing an RCA cleaning solution. Furthermore, the silicon nitride layer is formed by the SINGEN process. Therefore, the first and second silicon oxide layer and the silicon nitride layer can be etched together by the RCA cleaning solution.

Abstract: A method of making a gate structure includes the following steps. First, a gate is formed. Then, a first silicon oxide layer, a silicon nitride layer, and a second silicon oxide layer are formed to cover the gate from bottom to top. Later, a dry etching is performed to etch the second silicon oxide layer. After that, a wet etching is performed to etch the silicon nitride layer and the first silicon oxide layer. The aforesaid wet etching is performed by utilizing an RCA cleaning solution. Furthermore, the silicon nitride layer is formed by the SINGEN process. Therefore, the first and second silicon oxide layer and the silicon nitride layer can be etched together by the RCA cleaning solution.

Abstract: A wet cleaning process is provided. The wet cleaning process includes at least one first rinse process and a second rinse step. The first rinse step includes rinsing a substrate using deionized water containing CO2, and then draining the water containing CO2 to expose the substrate in an atmosphere of CO2. The second rinse step includes rinsing the substrate using deionized water containing CO2.

Abstract: A method of making a metal-metal capacitor is disclosed, in which a first metal layer, a first dielectric layer, a second metal layer, a second dielectric layer, and a third metal layer are formed in the order over a substrate; an upper capacitor is defined by etching using a first mask, wherein the stop of the etching can be controlled; a lower capacitor is defined by etching using a second mask; and an anti-reflective third mask is formed to cover the surface, and the capacitor border and metal interconnect conductive wire are defined, so as to make a metal-metal capacitor with a stable structure in a wide process window.

Abstract: A wet cleaning process is provided. The wet cleaning process includes at least one first rinse process and a second rinse step. The first rinse step includes rinsing a substrate using deionized water containing CO2, and then draining the water containing CO2 to expose the substrate in an atmosphere of CO2. The second rinse step includes rinsing the substrate using deionized water containing CO2.

Abstract: An etching apparatus is described, including an etching chamber, a gas pipe, a gas distribution plate and a heater. The gas pipe is disposed above the etching chamber for delivering a gas to the exterior surface of the etching chamber. The gas distribution plate is disposed at the outlet of the gas pipe, including a plate body and an inner collar-shaped part thereon facing the outlet of the gas pipe. The inner collar-shaped part and the portion of the plate body around the inner collar-shaped part each has multiple through holes therein. The heater is disposed around the space between the gas pipe and the etching chamber for heating the gas flowing out of the gas distribution plate.

Abstract: An etching apparatus is described, including an etching chamber, a gas pipe, a gas distribution plate and a heater. The gas pipe is disposed above the etching chamber for delivering a gas to the exterior surface of the etching chamber. The gas distribution plate is disposed at the outlet of the gas pipe, including a plate body and an inner collar-shaped part thereon facing the outlet of the gas pipe. The inner collar-shaped part and the portion of the plate body around the inner collar-shaped part each has multiple through holes therein. The heater is disposed around the space between the gas pipe and the etching chamber for heating the gas flowing out of the gas distribution plate.