Abstract: A data processing circuit and a fault mitigating method are provided. The method is adapted for a memory having at least one fault bit. The memory provides a block for data storage. A difference between an output of a value of a plurality of bits input to at least one computing layer in a neural network and a correct value is determined. The bits are respectively considered the at least one fault bit. A repair condition is determined based on the difference. The repair condition includes a correspondence between a position where the fault bit is located in the block and at least one non-fault bit in the memory. A value of at least one non-fault bit of the memory replaces a value of the fault bit based on the repair condition.

Abstract: A data processing circuit and a fault mitigating method are provided. The method is adapted for a memory having at least one fault bit. The memory provides a block for data storage. A difference between an output of a value of a plurality of bits input to at least one computing layer in a neural network and a correct value is determined. The bits are respectively considered the at least one fault bit. A repair condition is determined based on the difference. The repair condition includes a correspondence between a position where the fault bit is located in the block and at least one non-fault bit in the memory. A value of at least one non-fault bit of the memory replaces a value of the fault bit based on the repair condition.

Abstract: A method for debugging a program, based on simulating an object program and comparing simulated waveforms with standard waveforms are applied in an electronic device. A simulated environment corresponding to the object program is established and multiple instructions from code of the object program are mapped against the standard waveforms. Trigger points are set in the object program, the object program is run from the trigger point and simulation waveforms are stored. The simulation waveforms are compared with the standard waveforms, and the location of a bug of the object program is found according a comparison. The bug may be resolved or cured. The electronic device utilizing the method is also disclosed.

Abstract: A method for debugging a program, based on simulating an object program and comparing simulated waveforms with standard waveforms are applied in an electronic device. A simulated environment corresponding to the object program is established and multiple instructions from code of the object program are mapped against the standard waveforms. Trigger points are set in the object program, the object program is run from the trigger point and simulation waveforms are stored. The simulation waveforms are compared with the standard waveforms, and the location of a bug of the object program is found according a comparison. The bug may be resolved or cured. The electronic device utilizing the method is also disclosed.

Abstract: An architecture for a microcontroller includes a microcontroller, a system memory, an instruction memory, a data memory, a first bus, and a second bus, where the first and second buses perform functions of a single bus. The microcontroller connects to both buses. The instruction memory and the data memory are connected to the first bus. The system memory is connected to the second bus. The microcontroller transmits and receives data to and from the instruction memory and the data memory through the first bus. The microcontroller transmits and receives data to and from the system memory through the second bus. The instruction memory and the data memory transmit and receive data to and from the system memory through the second bus connected to the first bus, avoiding delays caused by rights and priorities and arbitration of same.

Abstract: An architecture for a microcontroller includes a microcontroller, a system memory, an instruction memory, a data memory, a first bus, and a second bus, where the first and second buses perform functions of a single bus. The microcontroller connects to both buses. The instruction memory and the data memory are connected to the first bus. The system memory is connected to the second bus. The microcontroller transmits and receives data to and from the instruction memory and the data memory through the first bus. The microcontroller transmits and receives data to and from the system memory through the second bus. The instruction memory and the data memory transmit and receive data to and from the system memory through the second bus connected to the first bus, avoiding delays caused by rights and priorities and arbitration of same.

Abstract: A method for reducing memory size and amount of data accessed of a buffered-frame storage device in a video codec is provided. It is applicable to a codec compliant with a video encoding and decoding standard. When a block is decompressed, the block is stored in the buffered-frame storage device using either compression data or reconstructed data based on its encoded mode and the positions of its reference frames, or based on a topological pattern and a pre-determined memory capacity constraint. With this method, not only the memory size of the buffered-frame storage device, but also the computational complexity requirement for decoding compression data of reference frames is reduced. The present invention compromises among the buffered-frame memory size, amount of data accessed, and computational complexity requirement.

Abstract: A monitoring system including N cameras, a digital video recorder (DVR), a monitor, a remote controller, a receiver and a host is provided. N is a positive integer. The N cameras successively shoot N sceneries, and output N successive images accordingly. The DVR receives and stores the N successive images. The monitor displays a monitoring screen. The remote controller outputs a wireless remote signal. The receiver receives the wireless remote signal and outputs a wire transmit signal accordingly. The host controls the monitor to display at least the successive image in the monitoring screen. The host has an on screen display (OSD) program. When the controller receives the wire transmit signal, the host utilizes the OSD program to process the wire transmit signal to become a screen adjusting signal. The host adjusts the monitoring screen according to the screen adjusting signal.

Abstract: A remote controller is described. The remote controller can remote control a plurality of electrical equipments, e.g. digital video recorders, simultaneously or respectively. The remote controller includes a signal emitter, a memory, and a plurality of keys. The memory stores a plurality of controller identification codes, and the keys can select at least one of the controller identification codes and the same is sent to the electrical equipments through the signal emitter. The electrical equipment compares the controller identification code with an equipment identification code stored in the electrical equipment when the electrical equipment receives the controller identification code.

Abstract: A monitoring system including N cameras, a digital video recorder (DVR), a monitor, a remote controller, a receiver and a host is provided. N is a positive integer. The N cameras successively shoot N sceneries, and output N successive images accordingly. The DVR receives and stores the N successive images. The monitor displays a monitoring screen. The remote controller outputs a wireless remote signal. The receiver receives the wireless remote signal and outputs a wire transmit signal accordingly. The host controls the monitor to display at least the successive image in the monitoring screen. The host has an on screen display (OSD) program. When the controller receives the wire transmit signal, the host utilizes the OSD program to process the wire transmit signal to become a screen adjusting signal. The host adjusts the monitoring screen according to the screen adjusting signal.

Abstract: A method for reducing memory size and amount of data accessed of a buffered-frame storage device in a video codec is provided. It is applicable to a codec compliant with a video encoding and decoding standard. When a block is decompressed, the block is stored in the buffered-frame storage device using either compression data or reconstructed data based on its encoded mode and the positions of its reference frames, or based on a topological pattern and a pre-determined memory capacity constraint. With this method, not only the memory size of the buffered-frame storage device, but also the computational complexity requirement for decoding compression data of reference frames is reduced. The present invention compromises among the buffered-frame memory size, amount of data accessed, and computational complexity requirement.