Abstract: A voltage tracking circuit is provided. The voltage tracking circuit includes first and second P-type transistors and a control circuit. The drain of the first P-type transistor is coupled to a first voltage terminal. The gate and the drain of the second P-type transistor are respectively coupled to the first voltage terminal and a second voltage terminal. The control circuit is coupled to the first and second voltage terminals and generates a control voltage according to the first voltage and the second voltage. The sources of the first and second P-type transistors are coupled to an output terminal of the voltage tracking circuit, and the output voltage is generated at the output terminal. In response to the second voltage being higher than the first voltage, the control circuit generates the control signal to turn off the first P-type transistor.

Abstract: A method and system is disclosed for a wordline driver circuit used for a memory device. It has a logic stage operating between a ground voltage and a first supply voltage and generating a logic stage output signal swinging between the ground voltage and the first supply voltage. It also has a mid voltage stage, operating between a raised ground voltage and a second supply voltage during the programming process, and generating a mid voltage stage output that swings between the second supply voltage and the raised ground voltage. It then has a high voltage stage, operating between the raised ground voltage and a third supply voltage, and generating a wordline driver output swinging between the third supply voltage and the raised ground voltage based on the received mid voltage stage output.

Abstract: A method and system is disclosed for a wordline driver circuit used for a memory device. It has a logic stage operating between a ground voltage and a first supply voltage and generating a logic stage output signal swinging between the ground voltage and the first supply voltage. It also has a mid voltage stage, operating between a raised ground voltage and a second supply voltage during the programming process, and generating a mid voltage stage output that swings between the second supply voltage and the raised ground voltage. It then has a high voltage stage, operating between the raised ground voltage and a third supply voltage, and generating a wordline driver output swinging between the third supply voltage and the raised ground voltage based on the received mid voltage stage output.

Abstract: A memory programming control circuit is disclosed. The memory programming control circuit is connected to a memory cell via a data line for controlling a programming current in a programming operation of the memory cell. The memory programming control circuit includes a programming enable device connected to a positive power supply for selectively applying a pull-up current on the data line; and a self-latch module connected between the programming enable device and the memory cell for preventing the pull-up current from flowing to the memory cell through the data line, when the memory cell is programmed with a predetermined data bit.

Abstract: A memory programming control circuit is disclosed. The memory programming control circuit is connected to a memory cell via a data line for controlling a programming current in a programming operation of the memory cell. The memory programming control circuit includes a programming enable device connected to a positive power supply for selectively applying a pull-up current on the data line; and a self-latch module connected between the programming enable device and the memory cell for preventing the pull-up current from flowing to the memory cell through the data line, when the memory cell is programmed with a predetermined data bit.

Abstract: This invention provides a circuit and a method for producing a very low voltage power supply utilizing the band gap technology. The invention provides for a band gap circuit which can operate at a voltage as low as 1.2 volts using a low power process. The circuit makes use of a combination of NMOS and PMOS devices to develop the required voltage biases that allow the circuit to operate at the band gap voltage. This allows the circuit to operate at power supply voltages as low as 1.2 volts.

Abstract: A method and system for forming a programmable logic array from a plurality of read only memory cells. The interconnection of the first metal layer with a second metal layer results in the formation of a read only memory cell therebetween, such that a plurality of read only memory cells can be configured to form a programmable logic array. One or more of the read only memory cells may be programmed utilizing a particular contact via programming technique, resulting in a shortened turn-around-time, reduced read only memory cell size, and a reduction in the necessity of requiring additional masks for read only memory logical processes associated with the programmable logic array. The memory cells comprise mask ROM cells which do not require extra masks, and can be programmed utilizing via programming techniques. The utilization of a first and second metal layer in interconnection configuration for a ROM cell results in smaller cell size.

Abstract: A method and system for forming a programmable logic array from a plurality of read only memory cells. The interconnection of the first metal layer with a second metal layer results in the formation of a read only memory cell therebetween, such that a plurality of read only memory cells can be configured to form a programmable logic array. One or more of the read only memory cells may be programmed utilizing a particular contact via programming technique, resulting in a shortened turn-around-time, reduced read only memory cell size, and a reduction in the necessity of requiring additional masks for read only memory logical processes associated with the programmable logic array. The memory cells comprise mask ROM cells which do not require extra masks, and can be programmed utilizing via programming techniques. The utilization of a first and second metal layer in interconnection configuration for a ROM cell results in smaller cell size.

Abstract: A sense amplifier for detecting a logic state of a memory cell includes a voltage amplifier, a current mirror, and a feedback circuit. The voltage amplifier couples to the memory cell and the current mirror. The feedback circuit couples to the current mirror and an input of the sense amplifier. The feedback circuit can be implemented with a transistor, a switch, a transmission gate, or the like. The feedback circuit is selectively enabled to quickly charge or discharge the voltage at the input of the sense amplifier to a trip voltage of the sense amplifier. Whether charging or discharging is performed is dependent on the voltage then existing at the input node. The amount of charging and discharging current can also be based on other circuit considerations, such as the required charge time, and so on. When the voltage at the input reaches a predetermined voltage range, the feedback circuit is disabled.