Patents by Inventor Chien-Feng Chen

Chien-Feng Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240101784
    Abstract: A novel additive for recycling thermoset materials, its related recyclable thermoset composition and its application are disclosed. Specifically, the composition of the additive comprises at least one copolymer that has at least one carbamate group, at least one carbonate group and/or at least one urea group, and a number-average molecular weight of the copolymer is between 100 and 50,000 Da.
    Type: Application
    Filed: September 5, 2023
    Publication date: March 28, 2024
    Inventors: Chien-Hsin Wu, Ying-Chi Huang, Ying-Feng Lin, Wen-Chang Chen, Ho-Ching Huang, Ru-Jong Jeng
  • Patent number: 11937932
    Abstract: An acute kidney injury predicting system and a method thereof are proposed. A processor reads the data to be tested, the detection data, the machine learning algorithm and the risk probability comparison table from a main memory. The processor trains the detection data according to the machine learning algorithm to generate an acute kidney injury prediction model, and inputs the data to be tested into the acute kidney injury prediction model to generate an acute kidney injury characteristic risk probability and a data sequence table. The data sequence table lists the data to be tested in sequence according to a proportion of each of the data to be tested in the acute kidney injury characteristics. The processor selects one of the medical treatment data from the risk probability comparison table according to the acute kidney injury characteristic risk probability.
    Type: Grant
    Filed: July 8, 2022
    Date of Patent: March 26, 2024
    Assignees: TAICHUNG VETERANS GENERAL HOSPITAL, TUNGHAI UNIVERSITY
    Inventors: Chieh-Liang Wu, Chun-Te Huang, Cheng-Hsu Chen, Tsai-Jung Wang, Kai-Chih Pai, Chun-Ming Lai, Min-Shian Wang, Ruey-Kai Sheu, Lun-Chi Chen, Yan-Nan Lin, Chien-Lun Liao, Ta-Chun Hung, Chien-Chung Huang, Chia-Tien Hsu, Shang-Feng Tsai
  • Patent number: 7400373
    Abstract: A liquid crystal display (LCD) panel has a structure in which one of the thin film transistor (TFT) substrate and the color filter (CF) substrate has an indented pattern surface to contact or surround the end of the spacer, such that the friction between the spacers and indented pattern surface can be reduced, thus shifting of spacer to a wrong position can be avoided. A method of manufacturing such LCD panel is also disclosed.
    Type: Grant
    Filed: May 27, 2005
    Date of Patent: July 15, 2008
    Assignee: HannStar Display Corp.
    Inventors: Yung-Ho Chang, Ching-Chao Chang, Chien-Feng Chen
  • Publication number: 20060268214
    Abstract: A liquid crystal display (LCD) panel has a structure in which one of the thin film transistor (TFT) substrate and the color filter (CF) substrate has an indented pattern surface to contact or surround the end of the spacer, such that the friction between the spacers and indented pattern surface can be reduced, thus shifting of spacer to a wrong position can be avoided. A method of manufacturing such LCD panel is also disclosed.
    Type: Application
    Filed: May 27, 2005
    Publication date: November 30, 2006
    Inventors: Yung-Ho Chang, Ching-Chao Chang, Chien-Feng Chen
  • Patent number: 6817875
    Abstract: The invention is directed to a card edge connector. The card edge connector is electrically connected to a first circuit board for insertion of a second circuit board therein such that the second circuit board can electrically connect with the first circuit board. The second circuit board is secured within the card edge connector by means of an interference device disposed on one side of a support arm of the card edge connector. The top side of the interference device is at a height higher than the surface of the second circuit board. When the user desires to remove the second circuit board from the card edge connector, a force can be applied to the interference device to cause the two support arms to expand slightly outward, thereby permitting removal of the second circuit board and also eliminating the risk of easy breaking of free ends of the support arms associated with conventional card edge connectors.
    Type: Grant
    Filed: January 29, 2003
    Date of Patent: November 16, 2004
    Assignee: Molex Incorporated
    Inventors: Wei-Sheng Chang, Chien-Feng Chen
  • Patent number: 6776626
    Abstract: An electrical connector system is provided for a mobile phone which includes a lower housing disposed beneath a printed circuit board having a plurality of circuit traces on a bottom side thereof. The housing includes at least one cavity in an upper side thereof opposite the bottom side of the printed circuit board. A connector module is positionable in the cavity and includes a frame having at least one connector thereon. The connector has at least one flexible contact for surface-engaging a respective circuit trace on the bottom side of the printed circuit board. A complementary interengaging mounting structure is provided between the frame of the connector module and the lower phone housing to releasably mount the module in the cavity. Thereby the module easily can be selectively removed from the housing for repair or replacement purposes.
    Type: Grant
    Filed: March 4, 2003
    Date of Patent: August 17, 2004
    Assignee: Molex Incorporated
    Inventors: San-Shan Huang, Chien-Feng Chen
  • Publication number: 20030181078
    Abstract: An electrical connector system is provided for a mobile phone which includes a lower housing disposed beneath a printed circuit board having a plurality of circuit traces on a bottom side thereof. The housing includes at least one cavity in an upper side thereof opposite the bottom side of the printed circuit board. A connector module is positionable in the cavity and includes a frame having at least one connector thereon. The connector has at least one flexible contact for surface-engaging a respective circuit trace on the bottom side of the printed circuit board. A complementary interengaging mounting structure is provided between the frame of the connector module and the lower phone housing to releasably mount the module in the cavity. Thereby the module easily can be selectively removed from the housing for repair or replacement purposes.
    Type: Application
    Filed: March 4, 2003
    Publication date: September 25, 2003
    Inventors: San-Shan Huang, Chien-Feng Chen
  • Publication number: 20030148640
    Abstract: The invention is directed to a card edge connector. The card edge connector is electrically connected to a first circuit board for insertion of a second circuit board therein such that the second circuit board can electrically connect with the first circuit board. The second circuit board is secured within the card edge connector by means of an interference device disposed on one side of a support arm of the card edge connector. The top side of the interference device is at a height higher than the surface of the second circuit board. When the user desires to remove the second circuit board from the card edge connector, a force can be applied to the interference device to cause the two support arms to expand slightly outward, thereby permitting removal of the second circuit board and also eliminating the risk of easy breaking of free ends of the support arms associated with conventional card edge connectors.
    Type: Application
    Filed: January 29, 2003
    Publication date: August 7, 2003
    Inventors: Wei-Sheng Chang, Chien-Feng Chen
  • Publication number: 20020095754
    Abstract: In the present invention, setting apparatus for semiconductor equipment with multitude of chambers comprises a plurality of input devices coupled to a controlling system of the semiconductor equipment. The input devices are used for setting a maintain status of said chambers whereby said chambers can be available for a test process. A method for setting a plurality of statuses for a plurality of chambers in semiconductor equipment comprises setting a plurality of maintain statuses for the chambers and executing a plurality of test process in the chambers in the maintain statuses. To be specific, the setting step can simultaneously set an on-line status for each the chamber and the maintain status for other the chamber.
    Type: Application
    Filed: January 23, 2001
    Publication date: July 25, 2002
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Jack Yao, Ping-Chung Chung, Wei-Hsu Wang, Wei-Hao Lee, Chien-Feng Chen, Feng-Chi Chung, Kuen-Chu Chen, Ming-Che Ho
  • Publication number: 20020098600
    Abstract: In the present invention, setting apparatus for semiconductor equipment with multitude of chambers comprises a plurality of input devices coupled to a controlling system of the semiconductor equipment. The input devices are used for setting a maintain status of said chambers whereby said chambers can be available for a test process. A method for setting a plurality of statuses for a plurality of chambers in semiconductor equipment comprises setting a plurality of maintain statuses for the chambers and executing a plurality of test process in the chambers in the maintain statuses. To be specific, the setting step can simultaneously set an on-line status for each the chamber and the maintain status for other the chamber.
    Type: Application
    Filed: August 30, 2001
    Publication date: July 25, 2002
    Applicant: United Microelectronics Corp.
    Inventors: Jack Yao, Ping-Chung Chung, Wei-Hsu Wang, Wei-Hao Lee, Chien-Feng Chen, Feng-Chi Chung, Kuen-Chu Chen, Ming-Che Ho
  • Patent number: 6297528
    Abstract: A new method of fabricating a capacitor and PMOS devices in a mixed-mode product production in which a composite polysilicon top plate electrode is provided which prevents out-diffusion of dopant from the capacitor plate so that there is no auto-doping of the PMOS channel region is described. A layer of gate silicon oxide is provided over the surface of a semiconductor substrate. A first polysilicon layer is deposited overlying the gate silicon oxide layer. The first polysilicon layer and gate oxide layer are etched away where they are not covered by a mask to provide a PMOS gate electrode in a first region of the wafer and a bottom plate electrode for the capacitor in a second region of the wafer. A capacitor dielectric layer is deposited over the surface of the wafer. A composite polysilicon layer is deposited overlying the capacitor dielectric layer wherein the composite polysilcon layer comprises a lower doped polysilcon layer and an upper undoped polysilicon layer.
    Type: Grant
    Filed: March 6, 2000
    Date of Patent: October 2, 2001
    Inventors: Chien-Feng Chen, Shyh-Perng Chiou
  • Patent number: 6187080
    Abstract: An exhaust gas treatment apparatus for treating exhaust gas generated in semiconductor manufacturing processes. It includes a main pipe, a gas vortex means, a water vortex means, an U pipe and a discharge pipe. The main pipe transforms the exhaust gases to waste powder which are discharged out through the U pipe and the discharge pipe. The gas vortex means and water vortex means are located below the main pipe for generating annular and even downward gas flow and water flow at the outlet of the main pipe for preventing reflux of waste powder from entering into the main pipe. Waste powder thus won't deposit around the outlet. Scraper in the main pipe won't be stuck or deformed. Waste powder may be discharged out through the U pipe and discharge pipe smoothly and efficiently.
    Type: Grant
    Filed: August 9, 1999
    Date of Patent: February 13, 2001
    Assignee: United Microelectronics Inc.
    Inventors: Chung Ping-Chung, Lu Tsung-Lin, Chi-Hsien Chen, Jing-Yi Huang, Ju-Long Lee, Hunter Chung, Chien-Feng Chen
  • Patent number: 6033950
    Abstract: A new method of fabricating a capacitor and PMOS devices in a mixed-mode product production in which a composite polysilicon top plate electrode is provided which prevents out-diffusion of dopant from the capacitor plate so that there is no auto-doping of the PMOS channel region is described. A layer of gate silicon oxide is provided over the surface of a semiconductor substrate. A first polysilicon layer is deposited overlying the gate silicon oxide layer. The first polysilicon layer and gate oxide layer are etched away where they are not covered by a mask to provide a PMOS gate electrode in a first region of the wafer and a bottom plate electrode for the capacitor in a second region of the wafer. A capacitor dielectric layer is deposited over the surface of the wafer. A composite polysilicon layer is deposited overlying the capacitor dielectric layer wherein the composite polysilcon layer comprises a lower doped polysilcon layer and an upper undoped polysilicon layer.
    Type: Grant
    Filed: April 10, 1998
    Date of Patent: March 7, 2000
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Feng Chen, Shyh-Perng Chiou
  • Patent number: 5700740
    Abstract: A method is described for the prevention of the corrosion of interconnection wirings made of aluminum or aluminum-copper alloys in semiconductor integrated circuits. The invention uses a weak solution of NH.sub.4 OH to remove chlorine-containing residues that adhere to the sidewalls of the metal wirings patterned by reactive ion etching using chlorine-containing gaseous components, thus effectively quenching the chain reaction of aluminum electrochemical corrosion involving these chlorine-containing residues as an intermediary.
    Type: Grant
    Filed: March 25, 1996
    Date of Patent: December 23, 1997
    Assignee: Taiwan Semiconductor Manufacturing Company Ltd
    Inventors: Chien-Feng Chen, Huan Wen Wang
  • Patent number: 5647626
    Abstract: A non-vacuum semiconductor pick-up and transfer apparatus for handling semiconductor wafers. A flat tapered blade, with front and rear arcuate abutment surfaces adapted to hold a wafer, is provided. In use the blade is thrust between spaced wafers supported in a holder, lifted to retain the wafer between the abutment surfaces, and removed from the holder. The thin and tapered blade shape minimizes damage to the associated wafers in the event of a misalignment of the blade with the wafers.
    Type: Grant
    Filed: December 4, 1995
    Date of Patent: July 15, 1997
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Feng Chen, Jun-Sheng Hsu, Shih-Ming Pan, Knight-Tian Ou