Patents by Inventor Chien-Fu Chen

Chien-Fu Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250027227
    Abstract: Provided are a silicon carbide crystal growth device and a quality control method. The device includes: an annealing unit, a crystal growth unit, an atmosphere control unit, and a transport system; the atmosphere control unit provides a gas environment with low water, oxygen and nitrogen; the transport system transports a plurality of target objects after high-temperature purification by the annealing unit to the atmosphere control unit; after assembling silicon carbide seed crystal and silicon carbide powder in a graphite crucible and covering with thermal insulation material to form a container inside the atmosphere control unit, the transport system transports the container to the crystal growth unit. The method uses a weighing system in a chamber of the crystal growth unit to detect a weight change of silicon carbide seed crystal and silicon carbide powder during a crystal growth process through a plurality of weight sensors of the weighing system.
    Type: Application
    Filed: July 20, 2023
    Publication date: January 23, 2025
    Inventors: Yun-Fu Chen, Wei-Tse Hsu, Min-Sheng Chu, Chien-Li Yang, Tsu-Hsiang Lin, Yuan-Hong Huang
  • Publication number: 20240290771
    Abstract: An integrated circuit layout includes an upper active region comprising a first edge and a second edge extending along a first direction and respectively adjacent to an upper cell boundary by a distance D3 and a distance D4. A first gate line is disposed on the upper active region, extends along a second direction, and protrudes from the first edge by a length L3. A second gate line is disposed on the upper active region, extends along the second direction, and protrudes from the second edge by a length L4. Two dummy gate lines respectively extend along the second direction and are disposed at two sides of the upper active region and away from the upper cell boundary by a distance S. The first direction and the second direction are perpendicular. The distances D3, D4, S and the lengths L3 and L4 have the relationships: L3?D3?S, L4?D4?S, and D3?D4.
    Type: Application
    Filed: May 8, 2024
    Publication date: August 29, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Ruei-Yau Chen, Wei-Jen Wang, Kun-Yuan Wu, Chien-Fu Chen, Chen-Hsien Hsu
  • Patent number: 12066386
    Abstract: A sampling device is provided, including: a syringe barrel having an opening and a holding portion; a plunger body having a protruding wall and disposed in the syringe barrel through the opening, where the protruding wall has a first recessed portion; a spring disposed around the plunger body; and a fastening assembly having an engaging structure for engaging the fastening assembly with the holding portion, a groove rail for receiving the protruding wall of the plunger body and a fastening portion for limiting displacement of the plunger body. A semi-automatic sample feeding device is further provided and includes the sampling device and a flow control device, and a test paper detection system is also provided and includes the semi-automatic sample feeding device and a test paper device. The test paper detection system is able to stably introduce samples, suitable for large-volume samples, which meets the needs of point-of-care applications.
    Type: Grant
    Filed: May 12, 2021
    Date of Patent: August 20, 2024
    Assignee: National Taiwan University
    Inventors: Chien-Fu Chen, Shih-Jie Chen, Jia-Hui Lin
  • Patent number: 11984442
    Abstract: A layout includes a first and a second standard cells abutting along a boundary line. The first cell includes first fins. An edge of the first fins closest to and away from the boundary line by a distance D1. A first gate line over-crossing the first fins protrudes from the edge by a length L1. The second cell includes second fins. An edge of the second fins closest to and away from the boundary line by a distance D2. A second gate line over-crossing the second fins protrudes from the edge by a length L2. Two first dummy gate lines at two sides of the first fins and two second dummy lines at two sides of the second fins are respectively away from the boundary line by a distance S. The lengths L1 and L2, the distances S, D1 and D2 have the relationships: L1?D1?S, L2?D2?S, and D1?D2.
    Type: Grant
    Filed: April 8, 2022
    Date of Patent: May 14, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ruei-Yau Chen, Wei-Jen Wang, Kun-Yuan Wu, Chien-Fu Chen, Chen-Hsien Hsu
  • Publication number: 20240062924
    Abstract: A device, which is used to inspect the confinement boundary of a vertical spent nuclear fuel storage canister during operation, includes a vertical spent nuclear fuel storage unit, a lifting unit, a transferring unit and an inspection platform. The vertical spent nuclear fuel storage unit includes a vertical storage canister and a storage overpack. The vertical storage canister is configured for storing spent nuclear fuels, and the storage overpack is configured for storing the vertical storage canister. The lifting unit, connected with the vertical storage canister, is configured for lifting the vertical storage canister. The transferring unit, connected with the lifting unit, is configured for protecting the lifted vertical storage canister. The inspection platform, connected with the transferring unit and the storage overpack, is configured for creating more space with sufficient shielding for the usage of inspecting the confinement boundary of the vertical storage canister.
    Type: Application
    Filed: October 19, 2022
    Publication date: February 22, 2024
    Inventors: CHING-WEI YANG, KUEI-JEN CHENG, YING-WEI LIN, CHIEN-FU CHEN
  • Patent number: 11862622
    Abstract: An integrated circuit layout includes a first standard cell and a second standard cell. The first standard cell includes first gate lines arranged along a first direction and extending along a second direction. The second standard cell abuts to one side of the first standard cell along the second direction and includes second gate lines arranged along the first direction and extending along the second direction. A first gate line width of the first gate lines and a second gate line width of the second gate lines are different. A first cell width of the first standard cell and a second cell width of the second standard cell are integral multiples of a default gate line pitch of the first gate lines and the second gate lines. At least some of the second gate lines and at least some of the first gate lines are aligned along the second direction.
    Type: Grant
    Filed: June 16, 2021
    Date of Patent: January 2, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Kun-Yuan Wu, Wei-Jen Wang, Chien-Fu Chen, Chen-Hsien Hsu, Chien-Hung Chen, Chun-Hsien Lin
  • Publication number: 20230313280
    Abstract: An integrated nucleic acid loop-mediated isothermal amplification and mobile device system is provided and includes a main body and a power supply, where the 5 main body at least has a delivery unit, a heating unit and a control unit, the control unit is electrically connected to the delivery unit and the heating unit, and the power supply is electrically connected to the main body. A method for operating the integrated nucleic acid loop-mediated isothermal amplification and mobile device system is also provided.
    Type: Application
    Filed: October 14, 2022
    Publication date: October 5, 2023
    Inventors: Chien-Fu CHEN, Shou-Cheng WU, Shi-Jia CHEN, Yuh-Shiuan CHIEN, Wang-Huei SHENG
  • Publication number: 20230097189
    Abstract: A method for forming an integrated circuit layout including at least two standard cells having different cell heights is disclosed. The standard cells respectively have a well boundary to divide a PMOS region and an NMOS region. The standard cells are abutted side by side along their side edges in a way that the well boundaries of the cells are aligned along the row direction. The power rail and the ground rail of one of the standard cells are shifted to align and connect to the power rail and the ground rail of the other one of the standard cells.
    Type: Application
    Filed: July 19, 2022
    Publication date: March 30, 2023
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chien-Hung Chen, Ruei-Yau Chen, Wei-Jen Wang, Kun-Yuan Wu, Chien-Fu Chen, Chen-Hsien Hsu
  • Publication number: 20230099326
    Abstract: A method for forming an integrated circuit layout including at least two standard cells having different cell heights is disclosed. The standard cells respectively have a well boundary to divide a PMOS region and an NMOS region. The standard cells are abutted side by side along their side edges in a way that the well boundaries of the cells are aligned along the row direction. The power rail and the ground rail of one of the standard cells are extended in width or length to connect to the power rail and the ground rail of the other one of the standard cells.
    Type: Application
    Filed: July 21, 2022
    Publication date: March 30, 2023
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chien-Hung Chen, Ruei-Yau Chen, Wei-Jen Wang, Kun-Yuan Wu, Chien-Fu Chen, Chen-Hsien Hsu
  • Publication number: 20230095481
    Abstract: An integrated circuit layout includes a first and a second standard cells abutting along a boundary line. The boundary line and a first active region of the first standard cell include a distance D1. A first gate line on the first active region protrudes from the first active region by a length L1. The boundary line and a second active region of the second standard cell include a distance D2. A second gate line on the second active region protrudes from the second active region by a length L2. Two first dummy gate lines and two second dummy gate lines are disposed at two sides of the first active region and the second active region and are away from the boundary line by a distance S. The lengths L1 and L2, the distances S, D1 and D2 have the relationships: L1?D1?S, L2?D2?S, and D1?D2.
    Type: Application
    Filed: November 2, 2021
    Publication date: March 30, 2023
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Ruei-Yau Chen, Wei-Jen Wang, Kun-Yuan Wu, Chien-Fu Chen, Chen-Hsien Hsu
  • Publication number: 20230096645
    Abstract: A layout includes a first and a second standard cells abutting along a boundary line. The first cell includes first fins. An edge of the first fins closest to and away from the boundary line by a distance D1. A first gate line over-crossing the first fins protrudes from the edge by a length L1. The second cell includes second fins. An edge of the second fins closest to and away from the boundary line by a distance D2. A second gate line over-crossing the second fins protrudes from the edge by a length L2. Two first dummy gate lines at two sides of the first fins and two second dummy lines at two sides of the second fins are respectively away from the boundary line by a distance S. The lengths L1 and L2, the distances S, D1 and D2 have the relationships: L1?D1?S, L2?D2?S, and D1?D2.
    Type: Application
    Filed: April 8, 2022
    Publication date: March 30, 2023
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Ruei-Yau Chen, Wei-Jen Wang, Kun-Yuan Wu, Chien-Fu Chen, Chen-Hsien Hsu
  • Publication number: 20220344321
    Abstract: An integrated circuit layout includes a first standard cell and a second standard cell. The first standard cell includes first gate lines arranged along a first direction and extending along a second direction. The second standard cell abuts to one side of the first standard cell along the second direction and includes second gate lines arranged along the first direction and extending along the second direction. A first gate line width of the first gate lines and a second gate line width of the second gate lines are different. A first cell width of the first standard cell and a second cell width of the second standard cell are integral multiples of a default gate line pitch of the first gate lines and the second gate lines. At least some of the second gate lines and at least some of the first gate lines are aligned along the second direction.
    Type: Application
    Filed: June 16, 2021
    Publication date: October 27, 2022
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Kun-Yuan Wu, Wei-Jen Wang, Chien-Fu Chen, Chen-Hsien Hsu, Chien-Hung Chen, Chun-Hsien Lin
  • Publication number: 20220304665
    Abstract: A sampling device is provided, including: a syringe barrel having an opening and a holding portion; a plunger body having a protruding wall and disposed in the syringe barrel through the opening, where the protruding wall has a first recessed portion; a spring disposed around the plunger body; and a fastening assembly having an engaging structure for engaging the fastening assembly with the holding portion, a groove rail for receiving the protruding wall of the plunger body and a fastening portion for limiting displacement of the plunger body. A semi-automatic sample feeding device is further provided and includes the sampling device and a flow control device, and a test paper detection system is also provided and includes the semi-automatic sample feeding device and a test paper device. The test paper detection system is able to stably introduce samples, suitable for large-volume samples, which meets the needs of point-of-care applications.
    Type: Application
    Filed: May 12, 2021
    Publication date: September 29, 2022
    Applicant: National Taiwan University
    Inventors: Chien-Fu CHEN, Shih-Jie CHEN, Jia-Hui LIN
  • Patent number: 11368146
    Abstract: A delay cell includes a cascode transistor and an inverter. The cascode transistor is used to receive a control voltage to generate a bias current, and includes a source terminal, a drain terminal, and a gate terminal receiving the control voltage. The inverter is coupled to the cascode transistor and used to generate an output signal according to the bias current in response to an input signal.
    Type: Grant
    Filed: April 14, 2020
    Date of Patent: June 21, 2022
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Kun-Yuan Wu, Wei-Jen Wang, Chien-Fu Chen, Chen-Hsien Hsu, Yuan-Hui Chen, Cheng-Yang Tsai, Ruei-Yau Chen, Cheng-Tsung Ku, Zhi-Hong Huang, Yu-Lin Chen
  • Patent number: 11348847
    Abstract: The invention provides a testkey detection circuit, including a plurality of oscillators and a driving circuit. Each of the oscillators has an enable terminal, a voltage terminal and an output terminal, wherein the enable terminals are connected to a common enable terminal. The driving circuit receives the output terminals of the oscillators and increases a driving level of a selected one of the output terminals as a frequency output.
    Type: Grant
    Filed: January 16, 2019
    Date of Patent: May 31, 2022
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Kun-Yuan Wu, Wei-Jen Wang, Chien-Fu Chen, Chen-Hsien Hsu, Yuan-Hui Chen, Ruei-Yau Chen, Cheng-Tsung Ku, Zhi-Hong Huang, Cheng-Yang Tsai, Yu-Lin Chen
  • Patent number: 11131667
    Abstract: The present disclosure provides a paper-based vertical flow test platform including: a detection portion; a movable conjugation portion having an enzyme-labelled protein; and an absorbent portion. The present disclosure further provides a detection method by using the same. With the folding and sliding design, the present disclosure can reduce the volume of specimen fluids used, and prevent the interference problem. Also, a portable diagnostic test platform is provided with ease of use, lower cost, higher sensitivity and longer storage period to meet requirements of point-of-care for the fast, simple and stable detection.
    Type: Grant
    Filed: April 26, 2019
    Date of Patent: September 28, 2021
    Assignee: National Taiwan University
    Inventors: Chien-Fu Chen, Wen-Shin Yeh
  • Publication number: 20210288634
    Abstract: A delay cell includes a cascode transistor and an inverter. The cascode transistor is used to receive a control voltage to generate a bias current, and includes a source terminal, a drain terminal, and a gate terminal receiving the control voltage. The inverter is coupled to the cascode transistor and used to generate an output signal according to the bias current in response to an input signal.
    Type: Application
    Filed: April 14, 2020
    Publication date: September 16, 2021
    Inventors: Kun-Yuan Wu, Wei-Jen Wang, Chien-Fu Chen, Chen-Hsien Hsu, Yuan-Hui Chen, Cheng-Yang Tsai, Ruei-Yau Chen, Cheng-Tsung Ku, Zhi-Hong Huang, Yu-Lin Chen
  • Patent number: 11115033
    Abstract: A speed-up charge pump includes a first charge pump for receiving an up signal and a down signal in digital form to produce a first voltage control signal at an output node. Further, at least one speed-up phase detector includes a first circuit path to receive the up signal and delay the up signal by a predetermined delay as a delay up signal and operate the up signal and the delay up signal by AND logic into an auxiliary up signal; and a second circuit path to receive the down signal and delay the down signal by the predetermined delay as a delay down signal and operate the down signal and the delay down signal by AND logic into an auxiliary down signal. A second charge pump is respectively receiving the auxiliary up and down signals to produce a second voltage control signal also at the output node.
    Type: Grant
    Filed: October 7, 2020
    Date of Patent: September 7, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Kun-Yuan Wu, Wei-Jen Wang, Chien-Fu Chen, Cheng-Yang Tsai, Ruei-Yau Chen, Yu-Lin Chen
  • Publication number: 20210067042
    Abstract: A multi-phase switched capacitor power converter and a control method thereof are disclosed. The multi-phase switched capacitor power converter includes a first phase converting circuit and a second phase converting circuit. The first phase converting circuit and the second phase converting circuit include switches and a flying capacitor respectively. The switches are coupled in series and there are a first node and a second node between the switches. The flying capacitor is coupled to the first node and the second node. When the first phase converting circuit is in an operating mode and the second phase converting circuit is in a standby mode, the control method controls a part of the switches in the second phase converting circuit continuously conducted to charge the flying capacitor.
    Type: Application
    Filed: August 12, 2020
    Publication date: March 4, 2021
    Inventors: Hsien-Cheng LIU, Chien-Fu CHEN
  • Publication number: 20200345923
    Abstract: Provided is a manual centrifugal device, including a rotating platform disposed with a rotating shaft, and a plurality of blood storage tubes fixed to the rotating platform at a regular intervals, wherein the rotating platform and the plurality of blood storage tubes rotate relative to the plane of placement during centrifugation. Further provided is a method for separating blood. The centrifugal device is driven manually to centrifugally separate blood cells and blood plasma, thereby greatly reducing the medical cost of blood examination and providing a more convenient and simple blood separation method for the low-resource areas.
    Type: Application
    Filed: December 9, 2019
    Publication date: November 5, 2020
    Inventors: Chien-Fu Chen, Chao-Hsuan Liu